Verilog Formal Verification

Open-source Verilog projects categorized as Formal Verification
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Topics: risc-v Verilog Cpu Riscv Rv32i
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Verilog Formal Verification Projects

  • RISC-V

    Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

    • Project mention: Prototype Demonstration of a 32-bit RISC-V Softcore with FreeRTOS | /r/FPGA | 2023-06-03

    The project repository and the details about the paper can be found here.

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NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

Index

Project Stars
1 RISC-V 44

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