ITA-CORES VS riscv

Compare ITA-CORES vs riscv and see what are their differences.

ITA-CORES

RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32 (by FelipeFFerreira)
Chip Framework physical-design physical-design-automation risc-v Rv32i Asic femtorv32
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riscv

RISC-V CPU Core (RV32IM) (by ultraembedded)
risc-v Cpu Verilog Fpga Verilator Rv32im Rv32i riscv-linux pipeline-processor Asic Verification
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ITA-CORES riscv
1 2
34 1,040
- -
8.7 1.8
6 months ago over 2 years ago
Verilog Verilog
GNU General Public License v3.0 or later BSD 3-clause "New" or "Revised" License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

ITA-CORES

Posts with mentions or reviews of ITA-CORES. We have used some of these posts to build our list of alternatives and similar projects.

riscv

Posts with mentions or reviews of riscv. We have used some of these posts to build our list of alternatives and similar projects.

What are some alternatives?

When comparing ITA-CORES and riscv you can also consider the following projects:

biriscv - 32-bit Superscalar RISC-V CPU

openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

zipcpu - A small, light weight, RISC CPU soft core

Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog

uhd - The USRP™ Hardware Driver Repository

riscv-cores-list - RISC-V Cores, SoC platforms and SoCs

livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

airisc_core_complex - Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.

dpll - A collection of phase locked loop (PLL) related projects

vgasim - A Video display simulator

ice40_power - Power analysis of the ICE40UP5K-SG48 devices

riscv vs biriscv riscv vs openlane riscv vs darkriscv riscv vs zipcpu riscv vs Toast-RV32i riscv vs uhd riscv vs riscv-cores-list riscv vs livehd riscv vs airisc_core_complex riscv vs dpll riscv vs vgasim riscv vs ice40_power