riscv VS ice40_power

Compare riscv vs ice40_power and see what are their differences.

riscv

RISC-V CPU Core (RV32IM) (by ultraembedded)
risc-v Cpu Verilog Fpga Verilator Rv32im Rv32i riscv-linux pipeline-processor Asic Verification
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ice40_power

Power analysis of the ICE40UP5K-SG48 devices (by tinyvision-ai-inc)
ice40 Fpga lattice-fpga Verilog Power
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riscv ice40_power
2 2
1,040 20
- -
1.8 0.0
over 2 years ago over 3 years ago
Verilog Verilog
BSD 3-clause "New" or "Revised" License MIT License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

riscv

Posts with mentions or reviews of riscv. We have used some of these posts to build our list of alternatives and similar projects.

ice40_power

Posts with mentions or reviews of ice40_power. We have used some of these posts to build our list of alternatives and similar projects.
  • iCE40 power consumption question
    1 project | /r/FPGA | 30 Jun 2021
    You can probably extrapolate from the numbers here.
  • Using an FPGA for low-power device with fast image acquisition
    1 project | /r/FPGA | 12 Apr 2021
    Aside from the points that /u/captain_wiggles_ pointed out, this is an application which ice40 FPGAs were actually designed for. They are low power (example) and have some features specifically designed for video applications, such as (sub)LVDS inputs and "outputs." Depending on your specs, one of these FPGAs could be a good choice (and you get a nice FOSS toochain as a bonus).

What are some alternatives?

When comparing riscv and ice40_power you can also consider the following projects:

biriscv - 32-bit Superscalar RISC-V CPU

a2o - The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue. It is now being updated for compliancy and integration into open projects.

openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

zipcpu - A small, light weight, RISC CPU soft core

Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog

uhd - The USRP™ Hardware Driver Repository

riscv-cores-list - RISC-V Cores, SoC platforms and SoCs

livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

airisc_core_complex - Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.

dpll - A collection of phase locked loop (PLL) related projects

vgasim - A Video display simulator

riscv vs biriscv ice40_power vs a2o riscv vs openlane riscv vs darkriscv riscv vs zipcpu riscv vs Toast-RV32i riscv vs uhd riscv vs riscv-cores-list riscv vs livehd riscv vs airisc_core_complex riscv vs dpll riscv vs vgasim