serv
learn-fpga
| serv | learn-fpga | |
|---|---|---|
| 20 | 22 | |
| 1,254 | 2,337 | |
| - | - | |
| 7.6 | 7.3 | |
| 24 days ago | 18 days ago | |
| Verilog | C++ | |
| ISC License | BSD 3-clause "New" or "Revised" License |
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serv
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RISC-V support in Android just got a big setback
> Right now, most devices on the market do not support the C extension
This is not true and easily verifiable.
The C extension is defacto required, the only cores that don't support it are special purpose soft cores.
C extension in the smallest IP available core https://github.com/olofk/serv?tab=readme-ov-file
Supports M and C extensions https://github.com/YosysHQ/picorv32
Another sized optimized core with C extension support https://github.com/lowrisc/ibex
C extension in the 10 cent microcontroller https://www.wch-ic.com/products/CH32V003.html
This one should get your goat, it implements as much as it can using only compressed instructions https://github.com/gsmecher/minimax
- SERV – The SErial RISC-V CPU
- SERV: A bit-serial RISC-V core
- SERV – open-source Tiny SErial RISC-V CPU
- How many LUT for an 8 bit CPU?
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Minimax: a Compressed-First, Microcoded RISC-V CPU
In short: it works, though the implementation lacks the crystal clarity of FemtoRV32 and PicoRV32. The core is larger than SERV but has higher IPC and (very arguably) a more conventional implementation. The compressed instruction set is easier to expand into regular RV32I instructions than it is to execute directly.
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Apple to Move a Part of Its Embedded Cores to RISC-V
https://github.com/olofk/serv
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I have created a Reddit community about PicoBlaze soft processor...
As for the size advantage: this mattered more when LUTs were precious and when PicoBlaze's competition was either similarly unorthodox (J1 Forth CPU) or several times larger (MicroBlaze). Nowadays, there are very small RISC-V cores like FemtoRV32 Quark or SERV. RISC-V benefits from mainstream open-source tooling and has momentum that's hard to beat.
- Microchip to develop 12-core RISC-V processor for NASA
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RISC-V announces first new specifications of 2022 adding to 16 ratified in 2021
The RISC-V spec does allow non-trapping behavior and SeRV in particular has non-trapping behavior, which is an important part of how it can fit into 200 4-input LUTs.
https://github.com/olofk/serv#good-to-know
learn-fpga
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FPGA Dev Boards for $150 or Less
I've followed this tutorial recently, and it's amazing:
https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/...
The author includes detailed instruction for how to build a micro-controller in Verilog on an icestick, starting from a very simple blinker all the way to a functional RISC-V core.
My other suggestion would be: for most of the toolchain, skip your package manager and directly install the binary artifacts published on this Github repo:
https://github.com/YosysHQ/oss-cad-suite-build
You'll spare yourself a world of pain.
- Top Ten Fallacies About RISC-V (David Patterson)
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What are the best learning resources for a beginner?
You might want to look at https://github.com/BrunoLevy/learn-fpga
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First FPGA Board
Lattice Icestick is pretty cheap and has just enough LUTs to run a small riscv. Also check out https://github.com/BrunoLevy/learn-fpga
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My first Risc-V core in FPGA
Thanks Bruno Levy
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How to Emulate a CPU on an FPGA
These are good starting points: https://github.com/BrunoLevy/learn-fpga/ and, from there, https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/README.md.
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PicoBlaze in Verilog / Vivado
The best point-of-entry for "tiny" MCUs these days is FemtoRV32-Quark or SERV. I also maintain my own small RISC-V core (Minimax), though it's early on in graduating from "experiment" to "real design".
- looking for ideas for a small project using digilent pmod on xilinx zynq 7 series fpga using hdl (verilog).
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Embedded Systems Weekly #125
Rust blinky on RISC-V soft core If you were looking for, an introduction example of an embedded Rust program, running on a RISC-V soft core, check out this blinky that is using the FemtoRV .
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Minimax: A Compressed-First, Microcoded RISC-V CPU
Nope - that's all there is.
It's possible to be incredibly expressive in Verilog and VHDL. This implementation is written in VHDL, which has an outdated reputation for being long-winded.
Also worth a look: FemtoRV32 Quark [0], which is written in Verilog.
[0]: https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/...
What are some alternatives?
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
riscv-v-spec - Working draft of the proposed RISC-V V vector extension
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
bubbleos
IronOS - Open Source Soldering Iron firmware
wain - WebAssembly implementation from scratch in Safe Rust with zero dependencies
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
openfpga - Open FPGA tools
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
rust-wasm - A simple and spec-compliant WebAssembly interpreter
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
Lifeslice - Automatically take webcam pics, screenshot, and other metrics throughout the day.