Minimax: A Compressed-First, Microcoded RISC-V CPU

• minimax

  14 195 2.9 Verilog

  Minimax: a Compressed-First, Microcoded RISC-V CPU

• learn-fpga

  22 2,367 7.3 C++

  Learning FPGA, yosys, nextpnr, and RISC-V

Nope - that's all there is.

It's possible to be incredibly expressive in Verilog and VHDL. This implementation is written in VHDL, which has an outdated reputation for being long-winded.

Also worth a look: FemtoRV32 Quark [0], which is written in Verilog.

[0]: https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/...

• InfluxDB

  www.influxdata.com featured

  Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  

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