reuse-tool
reuse is a tool for compliance with the REUSE recommendations. (by fsfe)
fusesoc
Package manager and build abstraction tool for FPGA/ASIC development (by olofk)
| reuse-tool | fusesoc | |
|---|---|---|
| 10 | 12 | |
| 345 | 1,118 | |
| 1.4% | - | |
| 9.1 | 7.3 | |
| 4 days ago | 21 days ago | |
| Python | Python | |
| - | BSD 2-clause "Simplified" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
reuse-tool
Posts with mentions or reviews of reuse-tool.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-06-29.
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Releasing AGPL3 project: SPDX vs full notice text and other questions
The SPDX header is due to a project called REUSE, which is spearheaded by the FSF Europe. You can read more about the project here. Basically you just have to add the copyright header in the format
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License of the input data
I do add my personalized input data into the public repository where I upload my solutions. I add complete reuse-compatible licensing information to my files.
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How to license my code if a component is gpl?
For projects that include vendored libraries under different licenses, it is becoming common to use Debian's copyright file format to describe which licenses apply to which source files. The data is usually placed in a file called /.reuse/dep5 (see the FSFE's Reuse Software project). If you want to enable fine-grained license checks, you can also include a machine-readable SPDX-License-Identifier line in each file.
- REUSE SOFTWARE – make licensing easy for humans and machines alike
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Should I put license notices in all my source code files?
Check out https://reuse.software
- LwESP library for ESP32 and ESP8266
- Reuse Software Licensing
- Reuse: Make licensing easy for humans and machines alike
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README/HACKING.md does not specify license and copyright terms
Putting the copyright and licensing information in every file was very common, and FSFEs reuse has some interesting specifications if compliance is an issue (e.g. I do not fully understand what the OpenSSL license included in the app-ios/tutanota/include folder covers, which also includes a APL-licensed files) - but thats a different topic.
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Should I go with GPLv3?
No, but it's a good idea to mention the license you're using. You can use REUSE (https://github.com/fsfe/reuse-tool).
fusesoc
Posts with mentions or reviews of fusesoc.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-03-28.
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fusesoc VS vextproj - a user suggested alternative
2 projects | 28 Mar 2024
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Introduction to FPGAs
Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
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CI/CD for FPGA builds
Check out FuseSoC: https://github.com/olofk/fusesoc it can run Vivado builds for you (as well as many other tools). It may be less work to get FuseSoC setup then work out a CLI Vivado batch flow from scratch.
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Besides misterFPGA what else can I play with on a DE10-nano?
Also, the FuseSOC and LiteX projects both support the DE10 nano, and can be used to roll your own custom SOCs with RISC-V or OpenRISC cores.
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Why isn't all verification work done in Python
Integration with the dependency and build tool I use (FuseSoc) is clumsy.
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Using Python with Vivado Projects
The "fusesoc" project may be of interest to you.
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Any recommendations for an RTL "standard library"?
FuseSoC is an RTL package manager. It will automatically download the latest versions of required components when you build. It also comes with a bunch of great options for components here:
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What should a modern IP library look like?
Have to correct this slightly: I just heard of my first HDL package manager in this thread. FuseSOC: https://github.com/olofk/fusesoc - Thanks u/gac_cag!
- Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
- Industry development process?
What are some alternatives?
When comparing reuse-tool and fusesoc you can also consider the following projects:
spdx-license-matcher - A tool to match license text with SPDX license list using a an algorithm with finds close matches. It follows SPDX Matching guidelines to keep the substantial text as well as ignore the replaceable text for matching purposes.
litex - Build your hardware, easily!
degiro-trading-tracker - Simplified tracking of your investments
edalize - An abstraction library for interfacing EDA tools
opentitan - OpenTitan: Open source silicon root of trust
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
rocket-chip - Rocket Chip Generator
vcdvcd - Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
hdl - HDL libraries and projects
serv - SERV - The SErial RISC-V CPU