cheshire VS ApogeoRV

Compare cheshire vs ApogeoRV and see what are their differences.

cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6 (by pulp-platform)

ApogeoRV

A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions. (by GabbedT)
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cheshire ApogeoRV
1 1
107 13
10.3% -
7.6 9.3
3 days ago about 2 months ago
SystemVerilog SystemVerilog
GNU General Public License v3.0 or later MIT License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

cheshire

Posts with mentions or reviews of cheshire. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-05-08.
  • Cpu project
    2 projects | /r/RISCV | 8 May 2023
    If you want to see the difference in scale you may want to compare the Cheshire SoC (Linux capable) here

ApogeoRV

Posts with mentions or reviews of ApogeoRV. We have used some of these posts to build our list of alternatives and similar projects.
  • Need help with B.tech last year project! On cache memory controller design using verilog hdl
    1 project | /r/chipdesign | 19 Jan 2023
    I am designing a cache controller in SystemVerilog for my RISCV CPU, it's currently under verification so there are a lot of bugs, but you can take a look to the code (https://github.com/GabbedT/RV32-Apogeo/tree/main/Hardware/Memory%20System/Data%20Cache) and to the documentation (https://github.com/GabbedT/RV32-Apogeo/blob/main/Docs/data-cache.md) (not up to date). Take this just as an example because I'm simply a third year bachelor student and this is only a personal project (I'm not followed by a professor or anything like that) so it might not be the best way to implement a cache controller.

What are some alternatives?

When comparing cheshire and ApogeoRV you can also consider the following projects:

hdmi - Send video/audio over HDMI on an FPGA

KinnowCPU - CPU implementing the Limn2600 architecture.

friscv - RISCV CPU implementation in SystemVerilog

rp32 - RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).

pulpissimo - This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

riscv - RISC-V CPU Core (RV32IM)

libsv - An open source, parameterized SystemVerilog digital hardware IP library

BrianHG-DDR3-Controller - DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux