open-register-design-tool
PeakRDL-ipxact
| open-register-design-tool | PeakRDL-ipxact | |
|---|---|---|
| 2 | 1 | |
| 182 | 31 | |
| 1.6% | - | |
| 5.3 | 0.0 | |
| 9 months ago | about 1 month ago | |
| Verilog | Python | |
| Apache License 2.0 | GNU General Public License v3.0 only |
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open-register-design-tool
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Thoughts about SystemRDL ?
I have used this compiler (https://github.com/Juniper/open-register-design-tool/wiki/Running-Ordt) to generate a Python model to access registers (I use Python on embedded Linux to read/write registers over SPI to the device).
- Auto Generate Header Files
PeakRDL-ipxact
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PeakRDL-Regblock: A free & open source tool that generates SystemVerilog control & status registers (CSR) from SystemRDL
If you're interested register automation, be sure to check out some of my other projects: * systemrdl-compiler * Compiler front-end for the SystemRDL 2.0 language. Want to generate something yourself from SystemRDL input? No problem - use this language interpreter as your front-end. * PeakRDL-html * Generates dynamic and pretty looking HTML documentation * PeakRDL-ipxact * Import/export IP-XACT XML * PeakRDL-uvm * Generate a UVM register model * And a bunch of other random stuff under my SystemRDL GitHub project.
What are some alternatives?
rggen - Code generation tool for control and status registers
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
gf180mcu-pdk - PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
PeakRDL-html - Generate address space documentation HTML from compiled SystemRDL input
systemrdl-compiler - SystemRDL 2.0 language compiler front-end
OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems
biriscv - 32-bit Superscalar RISC-V CPU
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication