neorv32
ulx3s-toolchain
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| neorv32 | ulx3s-toolchain | |
|---|---|---|
| 77 | 1 | |
| 1,423 | 36 | |
| - | - | |
| 9.9 | 10.0 | |
| 5 days ago | over 3 years ago | |
| C | Shell | |
| BSD 3-clause "New" or "Revised" License | MIT License |
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neorv32
- An example of how to add the A ISA extension's LR/SC operations into an open-source architecture
- NEORV32 - A tiny, customizable and highly extensible MCU-class 32-bit RISC-V microcontroller-like SoC written in platform-independent VHDL
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Recommendations for RISC-V on FPGA
How about NEORV32?
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SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG
GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. this one is good but is written in VHDL though
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RISCV CPU using PL on Pynq Z2 Development Board
NEORV32 is an open source soft core and very well documented. I would recommend you to take a look at it and play around a bit. And it is certainly possible to have a soft core running on only the PL side without PS interference.
- A tiny 1-Wire controller for FPGAs (in VHDL)
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Anyone want to share some embedded projects they have done?
Maybe not a classic (whatever that means...) project, but I am working (together with others) on a RISC-V microcontroller for FPGAs: https://github.com/stnolting/neorv32
ulx3s-toolchain
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Where do I start with RISC-V/
Later on when you want some FPGA hardware a cheap open source option is the ULX3S from Radiona. That combines the Lattice ECP5 FPGA with some useful peripherals. It's used with the open source yosys and project trellis tools.
What are some alternatives?
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
iverilog - Icarus Verilog
linux-on-litex-vexriscv - Linux on LiteX-VexRiscv
picoMIPS - picoMIPS processor doing affine transformation
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
fpga-zynq - Support for Rocket Chip on Zynq FPGAs
serv - SERV - The SErial RISC-V CPU
linux-on-litex-rocket - Run 64-bit Linux on LiteX + RocketChip
openFPGALoader - Universal utility for programming FPGA
riscv-debug-dtm - 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.