libsv
ulm-on-ice
libsv | ulm-on-ice | |
---|---|---|
2 | 1 | |
19 | 2 | |
- | - | |
3.6 | 5.6 | |
about 2 years ago | about 1 year ago | |
SystemVerilog | SystemVerilog | |
MIT License | GNU General Public License v3.0 only |
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libsv
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Skid Buffer
https://github.com/bensampson5/libsv/blob/main/libsv/fifos/skid_buffer.svhttps://libsv.readthedocs.io/en/latest/skid_buffer.html
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What should a modern IP library look like?
If you're interested in checking that out here's the link to the GitHub page for LibSV: https://github.com/bensampson5/libsv.
ulm-on-ice
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Building your own computer with an FPGA
I used a Lattice ice40 FPGA (e.g. icebreaker) FPGA to implement a simple RISC microprocessor. For the hardware description I used SystemVerilog and an open source toolchain. The source code is on GitHub.
What are some alternatives?
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
FPGA-Video-Processing - Realtime video processing w/ Gaussian + Sobel Filters targeting Artix-7 FPGA
DFHDL - DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
BrianHG-DDR3-Controller - DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
riscv-simple-sv - A simple RISC V core for teaching
cheshire - A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
VeriGPU - OpenSource GPU, in Verilog, loosely based on RISC-V ISA
scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog
opentitan - OpenTitan: Open source silicon root of trust
basys3_fpga_sandbox - Learning the basics of Systemverilog, testbench and more.