libsv
An open source, parameterized SystemVerilog digital hardware IP library (by bensampson5)
oh
Verilog library for ASIC and FPGA designers (by aolofsson)
| libsv | oh | |
|---|---|---|
| 2 | 1 | |
| 19 | 1,080 | |
| - | - | |
| 3.6 | 4.0 | |
| about 2 years ago | 3 months ago | |
| SystemVerilog | Verilog | |
| MIT License | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
libsv
Posts with mentions or reviews of libsv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-11-06.
-
Skid Buffer
https://github.com/bensampson5/libsv/blob/main/libsv/fifos/skid_buffer.svhttps://libsv.readthedocs.io/en/latest/skid_buffer.html
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What should a modern IP library look like?
If you're interested in checking that out here's the link to the GitHub page for LibSV: https://github.com/bensampson5/libsv.
oh
Posts with mentions or reviews of oh.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-11-06.
What are some alternatives?
When comparing libsv and oh you can also consider the following projects:
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
DFHDL - DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
opentitan - OpenTitan: Open source silicon root of trust
cheshire - A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
VHDL_Lib - Library of VHDL components that are useful in larger designs.
ulm-on-ice - ULM (Ulm Lecture Machine) on ice40
FPGA-Video-Processing - Realtime video processing w/ Gaussian + Sobel Filters targeting Artix-7 FPGA
basys3_fpga_sandbox - Learning the basics of Systemverilog, testbench and more.