fusesoc
blinky
| fusesoc | blinky | |
|---|---|---|
| 12 | 2 | |
| 1,118 | 151 | |
| - | 2.0% | |
| 7.3 | 6.0 | |
| 22 days ago | 10 days ago | |
| Python | Tcl | |
| BSD 2-clause "Simplified" License | MIT License |
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fusesoc
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fusesoc VS vextproj - a user suggested alternative
2 projects | 28 Mar 2024
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Introduction to FPGAs
Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
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CI/CD for FPGA builds
Check out FuseSoC: https://github.com/olofk/fusesoc it can run Vivado builds for you (as well as many other tools). It may be less work to get FuseSoC setup then work out a CLI Vivado batch flow from scratch.
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Besides misterFPGA what else can I play with on a DE10-nano?
Also, the FuseSOC and LiteX projects both support the DE10 nano, and can be used to roll your own custom SOCs with RISC-V or OpenRISC cores.
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Why isn't all verification work done in Python
Integration with the dependency and build tool I use (FuseSoc) is clumsy.
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Using Python with Vivado Projects
The "fusesoc" project may be of interest to you.
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Any recommendations for an RTL "standard library"?
FuseSoC is an RTL package manager. It will automatically download the latest versions of required components when you build. It also comes with a bunch of great options for components here:
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What should a modern IP library look like?
Have to correct this slightly: I just heard of my first HDL package manager in this thread. FuseSOC: https://github.com/olofk/fusesoc - Thanks u/gac_cag!
- Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
- Industry development process?
blinky
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Besides misterFPGA what else can I play with on a DE10-nano?
Maybe start with blinking a LED and go from there.
- Programming a blinking LED
What are some alternatives?
litex - Build your hardware, easily!
de10-nano - Absolute beginner's guide to the de10-nano
edalize - An abstraction library for interfacing EDA tools
opentitan - OpenTitan: Open source silicon root of trust
neorv32-examples - Some neorv32 examples for Intel FPGA boards using Quartus II and SEGGER Embedded Studio for RISC-V.
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
rocket-chip - Rocket Chip Generator
vcdvcd - Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication