Wiki_MiSTer
fusesoc
Wiki_MiSTer | fusesoc | |
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15 | 12 | |
99 | 1,119 | |
- | - | |
10.0 | 7.3 | |
over 1 year ago | 8 days ago | |
Python | ||
- | BSD 2-clause "Simplified" License |
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Wiki_MiSTer
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OpenFPGA. The future of video game preservation
I think it's a bit rich to describe this as the 'future of video game preservation'.
The MiSTer project https://github.com/MiSTer-devel/Wiki_MiSTer/wiki more rightfully deserves that title. It's got a huge range of systems (across consoles, arcade and micro computers) and it's all GPL licenced. The base board is a Terasic DE10 Nano which is proprietary but all other hardware required is open source.
The MiSTeX project aims to make MiSTer portable across different FPGA platforms https://github.com/MiSTeX-devel so a DE10 Nano won't be mandatory enabling a new ecosystem of open hardware and commercial for profit solutions.
I take no issue with people wanting to make money in this space. I take great issue with trying to gatekeep system preservation behind a mostly closed system you stamp an 'open' moniker on.
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New!
Go to the source https://github.com/MiSTer-devel/Wiki_MiSTer/wiki that should have all the information you need and also https://misterfpga.org/ and https://discord.gg/4xKVg4XVYn
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Minimig v1.97itx 6MB
Cute, but I don't see the point relative to miSTer.
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How Does an FPGA Work?
The MiSTer project[0] is a wonderful introduction to a practical use case for FPGAs. It uses verilog to describe how the DE10-Nano chip should be set up to resemble various classic computers, arcade machines, and video game consoles. With a single device you can have an Apple II+, Super Street Fighter II Turbo, and a SNES. Currently it supports up to the PlayStation for console cores, which is probably the upper bounds for the DE10-Nano.
The entire project feels perfectly in line with hacker mentality and is exciting to watch grow. There's nothing like playing Super Metroid with an original SNES controller on a CRT at the end of the day.
[0] https://github.com/MiSTer-devel/Wiki_MiSTer/wiki
- straightforward question Regarding direct video
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An argument for a new standalone FPGA-based Amiga aimed at the retro community
I'd advice anyone interested to look at miSTer instead. That is open hardware proper and has a very mature ecosystem of cores, including Amiga.
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I really like the idea of the Amiga 500 Mini. Is it frustrating to side load programs on it? Do the companies frown on you putting roms on it (I can't imagine Mortal Kombat is fretting my Amiga rom)
Consider the miSTer as an open source hardware (in FPGA) alternative (minimig FPGA core).
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Loading games from USB drive connected to my ASUS router with SMB enabled
Have you followed the steps here https://github.com/MiSTer-devel/Wiki_MiSTer/wiki/Samba funily enoough google pointed me here.
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Advice on MiSTer arcade cabinet setup
Here https://github.com/MiSTer-devel/Wiki_MiSTer/wiki and https://misterfpga.org/ I assume you know about these links?
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Introduction to FPGAs
You can find a lot of old computers and game consoles implemented in FPGA here:
- https://github.com/MiSTer-devel/Wiki_MiSTer/wiki/Cores
fusesoc
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fusesoc VS vextproj - a user suggested alternative
2 projects | 28 Mar 2024
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Introduction to FPGAs
Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
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CI/CD for FPGA builds
Check out FuseSoC: https://github.com/olofk/fusesoc it can run Vivado builds for you (as well as many other tools). It may be less work to get FuseSoC setup then work out a CLI Vivado batch flow from scratch.
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Besides misterFPGA what else can I play with on a DE10-nano?
Also, the FuseSOC and LiteX projects both support the DE10 nano, and can be used to roll your own custom SOCs with RISC-V or OpenRISC cores.
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Why isn't all verification work done in Python
Integration with the dependency and build tool I use (FuseSoc) is clumsy.
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Using Python with Vivado Projects
The "fusesoc" project may be of interest to you.
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Any recommendations for an RTL "standard library"?
FuseSoC is an RTL package manager. It will automatically download the latest versions of required components when you build. It also comes with a bunch of great options for components here:
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What should a modern IP library look like?
Have to correct this slightly: I just heard of my first HDL package manager in this thread. FuseSOC: https://github.com/olofk/fusesoc - Thanks u/gac_cag!
- Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
- Industry development process?
What are some alternatives?
icesugar-nano - iCESugar-nano FPGA board (base on iCE40LP1K)
litex - Build your hardware, easily!
edalize - An abstraction library for interfacing EDA tools
oss-cad-suite-build - Multi-platform nightly builds of open source digital design and verification tools
opentitan - OpenTitan: Open source silicon root of trust
tensil - Open source machine learning accelerators
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
make_for_vivado - experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
fpga-tamagotchi - Tamagotchi P1 for Analogue Pocket and MiSTer
rocket-chip - Rocket Chip Generator