FPGA-SDcard-Reader
rggen
| FPGA-SDcard-Reader | rggen | |
|---|---|---|
| 1 | 3 | |
| 221 | 286 | |
| - | 4.2% | |
| 3.8 | 7.1 | |
| 8 months ago | 6 days ago | |
| Verilog | Ruby | |
| GNU General Public License v3.0 only | MIT License |
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FPGA-SDcard-Reader
rggen
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RgGen v0.28.0
I've released RgGen v0.28.0! https://github.com/rggen/rggen/releases/tag/v0.28.0 This release includes following updates.
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RgGen update (support C header file generation)
RgGen is a code generation tool for configuration and status registers. RgGen can generate SV/Verilog/VHDL RTL, UVM RAL model and Markdown documents from readable register map specifications. https://github.com/rggen/rggen
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RgGen update
I just released the latest RgGen v0.26.0! https://github.com/rggen/rggen/releases/tag/v0.26.0
What are some alternatives?
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
PeakRDL-uvm - Generate UVM register model from compiled SystemRDL input
open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
OpenROAD - OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
PeakRDL-ipxact - Import and export IP-XACT XML register models
sdspi - SD-Card controller, using either SPI, SDIO, or eMMC interfaces
vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
edalize - An abstraction library for interfacing EDA tools
rggen-sv-rtl - Common SystemVerilog RTL modules for RgGen
hdlConvertor - Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4