zbasic VS openarty

Compare zbasic vs openarty and see what are their differences.

zbasic

A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems (by ZipCPU)

openarty

An Open Source configuration of the Arty platform (by ZipCPU)
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zbasic openarty
4 6
40 116
- -
0.0 0.0
over 1 year ago 3 months ago
Verilog Verilog
- -
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

zbasic

Posts with mentions or reviews of zbasic. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-01-10.
  • AXI Quad SPI 3.2 Flash programming scripts
    5 projects | /r/FPGA | 10 Jan 2022
    Here's sort of a generic repo you can look at which might give you some ideas.
  • How do you successfully compile a working verilator package on Ubuntu?
    1 project | /r/ZipCPU | 27 Jul 2021
    Let me also point out that I rarely use Verilators -exe flag. I tend instead to build my designs in steps: 1) Run Verilator, 2) run make -f Vtoplvl.mk in the obj_dir directory, 3) turn my test script into an object file, and only then 4) link everything together into an executable. I've also been known for peeking at Verilator's internal variables during a simulation run--but that may be another topic entirely.
  • Need help with Objcopy for Verilog Hex File
    3 projects | /r/FPGA | 7 Jul 2021
    As examples: - Here's how I process libelf to provide me with an array of section pointers, each containing the address to load the values at - Here's where I then load the values into my design when I'm using an external loader via a debugging bus. - Here's another copy of the same, this time running from within Verilator rather than from within externally controlled logic.
  • How can I get Verilator to Prompt for User Input?
    3 projects | /r/FPGA | 19 Apr 2021
    The components found in ZBasic will split the stream into two. The key files you'll want there are dbluartsim.cpp and (again) netuart.cpp. To use dbluart, you'll need three pieces: First, you'll need to call setup() to set the baud rate, then once per clock cycle you'll want to call the operator() method--which is really just a rename for the tick() method.

openarty

Posts with mentions or reviews of openarty. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-06-11.
  • C++ Verification Testbench Best-Practice Resources?
    7 projects | /r/FPGA | 11 Jun 2023
    I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.
  • PPS detection/regeneration
    2 projects | /r/FPGA | 25 May 2022
    The repo is the example design. It was used by software, though, that's not (currently) posted. A lot of math went into the coefficients as well--that's all in the software.
  • AXI Quad SPI 3.2 Flash programming scripts
    5 projects | /r/FPGA | 10 Jan 2022
    Here's the flash controller repo I use. There's a flash controller in there for SPI, Dual SPI, and Quad SPI. The Dual and Quad SPI controllers need a device specific startup script to get them into the right mode. This script should be fairly well explained by the comments. You should find at least one of these controllers that works for you. More recent versions of the controller have a Wishbone arbiter within them -- they're just not checked in the repo yet. (DSPI, QSPI). This makes it so the design fully supports two two Wishbone ports: a config port by which you can send any value and the memory mapped read port. (You can't use both at the same time.)
  • Arty S7 - 2 different flash brands
    1 project | /r/FPGA | 26 Aug 2021
    You can compare my configuration file for the Spansion flash with my config file for the Micron flash to see that these are the only two hardware differences between the two
  • FPGA and Simulation tools for Risc-V design
    4 projects | /r/FPGA | 24 Dec 2020
    I'd then recommend Verilator for simulation testing--but only after your formal design checking is complete. You can find online C++ models of a QSPI flash, RAM, and a serial port which should be good enough to get you going here. When you are ready for more permanent storage, there's also a decent C++ model of an SD card (SPI only).

What are some alternatives?

When comparing zbasic and openarty you can also consider the following projects:

openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

zipcpu - A small, light weight, RISC CPU soft core

dpll - A collection of phase locked loop (PLL) related projects

riscv-arch-test

qspiflash - A set of Wishbone Controlled SPI Flash Controllers

wbicapetwo - Wishbone to ICAPE interface conversion

fpga_quick_ram_update - Quickly update a bitstream with new RAM contents

arrowzip - A ZipCPU based demonstration of the MAX1000 FPGA board

autofpga - A utility for Composing FPGA designs from Peripherals

riscv-formal - RISC-V Formal Verification Framework

wbuart32 - A simple, basic, formally verified UART controller