vunit
UVVM
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vunit | UVVM | |
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10 | 6 | |
682 | 326 | |
2.1% | - | |
8.2 | 6.1 | |
28 days ago | about 2 months ago | |
VHDL | VHDL | |
GNU General Public License v3.0 or later | Apache License 2.0 |
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vunit
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Software languages vs HDLs for verification
My goto tools for verification in VHDL are UVVM and VUnit
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Libero - Inefficient Simulations
I think the VUnit vivado example (https://github.com/VUnit/vunit/tree/master/examples/vhdl/vivado) may be a good starting point when working with Xilinx IP outside of an IDE.
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Books About Testing and Verification
I learned a lot from https://vunit.github.io/ I even became a better VHDL engineer from this fantastic project. It showed me things I did not know VHDL was capable of.
- A couple of questions for the experts
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Reference of verification IPs
Hey! I haven't seen anyone mention Vunit yet. Vunit has a verification components library with Master and Slave components for a decent amount of buses: Axi, Axi stream, Wishbone, Avalon, Uart. The code isn't 100% bullet proof but it is really useful for testing designs.
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SystemVerilog testbench library
I agree vunit is great but due to circumstances (you can see post above) I need the testbench to be purely SV (and vunit as you said wouldn't help with all of that, only some of it, as you have pointed out). When I refered to vunit I forgot to link the example: https://github.com/VUnit/vunit/tree/master/examples/verilog/uart/src . I referred more to tge fact it is self checking, and the tasks can be reused in ither tbs as well
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The Vivado 2021.2 is out thread
As for simulation, the last time I used it there were a lot of features not supported. Not sure where this is documented, but I know VUnit can't support it per https://github.com/VUnit/vunit/issues/209 .
- How do you do automated testing of your HDL?
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VHDL Testbench Library Comparison
Please consider adding simulator support to this comparison. For example, Vivado's xsim can't be used with VUnit.
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The simplest way to automate my testbench?
I think these two examples can help you get started. https://github.com/VUnit/vunit/tree/master/examples/vhdl/array_axis_vcs https://github.com/VUnit/vunit/tree/master/examples/vhdl/generate_tests/
UVVM
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Software languages vs HDLs for verification
Using the open source UVVM (Universal VHDL Verification Methodology) will allow you to write high level (transaction level) testbenches using commands like 'axistream_transmit(my_byte_array)'. UVVM includes a large range of open source interface access mechanisms like that (BFMs & Verification components) like AXI, AXI-lite, AXI-stream, Avalon, Avalon-stream, Ethernet, GMII, RGMII, I2C, SPI, SBI, UART, etc. You can check out my presentation from DVCon US 2022 on 'Bringing UVM to VHDL' to get an introduction to UVVM. There are also lots of different webinars available for free on various aspects of UVVM.
- Books About Testing and Verification
- Verilog Text Book Recommendations?
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Getting Into Verification
I don't have enough experience to comment on what you should do, but I haven't seen UVVM mentioned in this thread, which is a testbench library for VHDL. It has a lot of nice functions for value checking and logging, as well as BFMs for SPI, UART, I2C, etc.
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Using tool for HDL verification/simulation
UVVM is a good platform for VHDL testbenches.
What are some alternatives?
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
vc_axi
AXI4 - AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
ghdl - VHDL 2008/93/87 simulator
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
catapult-v3-smartnic-re - Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)
OsvvmLibraries - Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
fpga_puf - :key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
rust_hdl
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
wb2axip - Bus bridges and other odds and ends
VHDL-Guide - VHDL Guide