UVVM

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/ (by UVVM)
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uvvm.github.io
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UVVM Alternatives

Similar projects and alternatives to UVVM

  • vunit

    10 UVVM VS vunit

    VUnit is a unit testing framework for VHDL/SystemVerilog

  • AXI4

    4 UVVM VS AXI4

    AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

  • WorkOS

    The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

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  • vc_axi

    1 UVVM VS vc_axi
NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better UVVM alternative or higher similarity.
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UVVM reviews and mentions

Posts with mentions or reviews of UVVM. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-02-11.
  • Software languages vs HDLs for verification
    3 projects | /r/FPGA | 11 Feb 2023
    Using the open source UVVM (Universal VHDL Verification Methodology) will allow you to write high level (transaction level) testbenches using commands like 'axistream_transmit(my_byte_array)'. UVVM includes a large range of open source interface access mechanisms like that (BFMs & Verification components) like AXI, AXI-lite, AXI-stream, Avalon, Avalon-stream, Ethernet, GMII, RGMII, I2C, SPI, SBI, UART, etc. You can check out my presentation from DVCon US 2022 on 'Bringing UVM to VHDL' to get an introduction to UVVM. There are also lots of different webinars available for free on various aspects of UVVM.
  • Books About Testing and Verification
    2 projects | /r/FPGA | 25 Jan 2023
  • Verilog Text Book Recommendations?
    3 projects | /r/Verilog | 15 Feb 2022
  • Getting Into Verification
    1 project | /r/FPGA | 31 May 2021
    I don't have enough experience to comment on what you should do, but I haven't seen UVVM mentioned in this thread, which is a testbench library for VHDL. It has a lot of nice functions for value checking and logging, as well as BFMs for SPI, UART, I2C, etc.
  • Using tool for HDL verification/simulation
    1 project | /r/FPGA | 27 Apr 2021
    UVVM is a good platform for VHDL testbenches.
  • A note from our sponsor - WorkOS
    workos.com | 23 Apr 2024
    The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning. Learn more →

Stats

Basic UVVM repo stats
6
326
6.1
about 2 months ago

UVVM/UVVM is an open source project licensed under Apache License 2.0 which is an OSI approved license.

The primary programming language of UVVM is VHDL.

Popular Comparisons

  1. UVVM VS vunit
  2. UVVM VS vc_axi

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