UVVM
UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/ (by UVVM)
vc_axi
By VUnit
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
UVVM
Posts with mentions or reviews of UVVM.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-02-11.
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Software languages vs HDLs for verification
Using the open source UVVM (Universal VHDL Verification Methodology) will allow you to write high level (transaction level) testbenches using commands like 'axistream_transmit(my_byte_array)'. UVVM includes a large range of open source interface access mechanisms like that (BFMs & Verification components) like AXI, AXI-lite, AXI-stream, Avalon, Avalon-stream, Ethernet, GMII, RGMII, I2C, SPI, SBI, UART, etc. You can check out my presentation from DVCon US 2022 on 'Bringing UVM to VHDL' to get an introduction to UVVM. There are also lots of different webinars available for free on various aspects of UVVM.
- Books About Testing and Verification
- Verilog Text Book Recommendations?
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Getting Into Verification
I don't have enough experience to comment on what you should do, but I haven't seen UVVM mentioned in this thread, which is a testbench library for VHDL. It has a lot of nice functions for value checking and logging, as well as BFMs for SPI, UART, I2C, etc.
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Using tool for HDL verification/simulation
UVVM is a good platform for VHDL testbenches.
vc_axi
Posts with mentions or reviews of vc_axi.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-02-15.
What are some alternatives?
When comparing UVVM and vc_axi you can also consider the following projects:
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
AXI4 - AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components