verilog-ethernet
Verilog Ethernet components for FPGA implementation (by alexforencich)
FPGA_RealTime_and_Static_Sobel_Edge_Detection
Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images (by AngeloJacobo)
| verilog-ethernet | FPGA_RealTime_and_Static_Sobel_Edge_Detection | |
|---|---|---|
| 32 | 3 | |
| 1,916 | 36 | |
| - | - | |
| 8.8 | 0.0 | |
| about 2 months ago | over 2 years ago | |
| Verilog | Verilog | |
| MIT License | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
verilog-ethernet
Posts with mentions or reviews of verilog-ethernet.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-05-21.
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Quartus Tcl Build Script
Tcl, not sure, but I have done it with makefiles. See https://github.com/alexforencich/verilog-ethernet/tree/master/example/C10LP/fpga.
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Using Si5324 as a clock generator on virtex-7 board
For that part I think you need to use the software from silicon labs (might be skyworks now) to generate the stuff you need to write to the registers. Then, you can use something like https://github.com/alexforencich/verilog-i2c/blob/master/rtl/i2c_init.v. See https://github.com/alexforencich/verilog-ethernet/tree/master/example/HTG9200/fpga_10g for an example that targets the Si5341 specifically.
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DE2-115 Ethernet Network Setup
For a personal project I'm trying to send data via Ethernet from my laptop into the FPGA, where it has some filtering and other processing done to it, then back into my laptop. I've been trying to get this repo to work, but there's a problem: my ancient macbook can't run Quartus, so I need to use campus PCs to build the project and program the board, but I don't have permissions to successfully run the makefiles that build the project.
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ROS 2 Humble in AMD KR260 with Yocto
No there's none. Not in this post at least, but it certain is being used. If you're interested in that, follow my progress at https://github.com/alexforencich/verilog-ethernet/issues/146 (or stay tuned/reach out to Acceleration Robotics for early previews and support) for a 10G NIC on the KR260.
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Choice of LFSR When implementing the ARP Cache in a UDP Stack
So, im trying to understand the UDP implementation in verilog-ethernet. In particular I am looking into the ARP Cache and have a query.
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Preference for Combinational or Sequential design?
I've been studying u/alexforencich's ethernet library since I'm working on a similar project. I've been noting his interesting design style. When I think about a solution for a problem, I immediately naturally thing about a sequential design whereas he has tons of combination logic in his designs.
- Are there any free/open source Lattice ECP5 Ethernet MAC IP Cores?
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Verilog Question- Setting a register concurrently twice in always block
I was studying Alex Forencich's FCS verilog and noticed the following always block:
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LiteX SGMII support
This repo support the VCU108 for a Verilog ethernet connection: https://github.com/alexforencich/verilog-ethernet
- Stream data into FPGA from PC
FPGA_RealTime_and_Static_Sobel_Edge_Detection
Posts with mentions or reviews of FPGA_RealTime_and_Static_Sobel_Edge_Detection.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-05-09.
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Sobel edge detection
Hi, you might be interested on having a look at this project. The main RTL for the convolution is in sobel_convolution.v
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Share some github FPGA projects (bonus if they include C++, Python, or other files)
I posted this project on this sub three weeks ago,
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Real-Time Sobel Edge Detection using FPGA (repo link in the comments)
Project repository
What are some alternatives?
When comparing verilog-ethernet and FPGA_RealTime_and_Static_Sobel_Edge_Detection you can also consider the following projects:
corundum - Open source FPGA-based NIC and platform for in-network compute
litex - Build your hardware, easily!
SpinalHDL - Scala based HDL
FPGA_OV7670_Camera_Interface - Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps
embox - Modular and configurable OS for embedded applications
SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)
cocotbext-axi - AXI interface modules for Cocotb
ULX3S_FPGA_Camera_Streaming - Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board
satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
verilog-ethernet vs corundum
FPGA_RealTime_and_Static_Sobel_Edge_Detection vs litex
verilog-ethernet vs litex
FPGA_RealTime_and_Static_Sobel_Edge_Detection vs SpinalHDL
verilog-ethernet vs SpinalHDL
FPGA_RealTime_and_Static_Sobel_Edge_Detection vs FPGA_OV7670_Camera_Interface
verilog-ethernet vs embox
FPGA_RealTime_and_Static_Sobel_Edge_Detection vs SBusFPGA
verilog-ethernet vs cocotbext-axi
FPGA_RealTime_and_Static_Sobel_Edge_Detection vs ULX3S_FPGA_Camera_Streaming
verilog-ethernet vs satcat5
FPGA_RealTime_and_Static_Sobel_Edge_Detection vs satcat5