Verilog pipelined

Open-source Verilog projects categorized as pipelined
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Topics: Verilog ov7670 sobel-edge-detector icestudio ulx3s
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Verilog pipelined Projects

  • FPGA_RealTime_and_Static_Sobel_Edge_Detection

    Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

    • Project mention: Sobel edge detection | /r/FPGA | 2023-05-09

    Hi, you might be interested on having a look at this project. The main RTL for the convolution is in sobel_convolution.v

  • ULX3S_FPGA_Sobel_Edge_Detection_OV7670

    Verilog design files and Icestudio file for Sobel Edge Detection with OV7670 camera using ULX3S FPGA Board

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NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

Index

Project Stars
1 FPGA_RealTime_and_Static_Sobel_Edge_Detection 34
2 ULX3S_FPGA_Sobel_Edge_Detection_OV7670 14

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