vcdvcd
hdl_checker
| vcdvcd | hdl_checker | |
|---|---|---|
| 1 | 4 | |
| 48 | 184 | |
| - | - | |
| 5.9 | 0.0 | |
| 4 months ago | 5 months ago | |
| Python | Python | |
| GNU General Public License v3.0 or later | GNU General Public License v3.0 only |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
vcdvcd
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Running CLI packages
I want to run this package from Spyder IDE (or Jupyter Notebook) on my Anaconda installation. I can install the package from PyPI just fine. However, from the documentation it is designed to be run from CLI. So, when given the command "vcdcat x.vcd" it should dump the contents to the command line. I tried writing this command in Anaconda prompt
hdl_checker
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Any better options than Sigasi?
I've written a LSP that uses modelsim, ghdl or Vivado to do error checking: https://github.com/suoto/hdl_checker
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What Editor is Everyone Using for FPGA design? (2021)
NeoVim + CoC + hdl_checker
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VHDL native lsp
As others mentioned, rust_hdl and ghdl ls are worth checking out. If your project has both VHDL and Verilog/SystemVerilog, might be worth checking https://github.com/suoto/hdl_checker (disclaimer, I'm the author). It's got less LS features than the other two but if you use it with modelsim it'll provide mixed language syntax check.
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IDE / Editor of choice
Specifically for HDL-files a lot of progress has been made in the last couple of years on lsp-mode and external LSP servers for code analysis of both VHDL and SystemVerilog. For SV I use the https://github.com/suoto/hdl_checker server that passes the code you are working on live to the Linting engine in Questa/ModelSim and marks the warning lines in the editor. It's nice to get immediate feedback on missing semicolons etc. although it still has a hard time handling large projects.
What are some alternatives?
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
completor.vim - Async completion framework made ease.
cocotb-bus - Pre-packaged testbenching tools and reusable bus interfaces for cocotb
rust_hdl
PlatformIO - Your Gateway to Embedded Software Development Excellence :alien:
veridian - A SystemVerilog Language Server
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
pymtl3 - Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
edalize - An abstraction library for interfacing EDA tools