riscv
psram-tang-nano-9k
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| riscv | psram-tang-nano-9k | |
|---|---|---|
| 1 | 5 | |
| 742 | 16 | |
| - | - | |
| 1.0 | 4.1 | |
| over 1 year ago | 5 months ago | |
| Verilog | Verilog | |
| BSD 3-clause "New" or "Revised" License | Apache License 2.0 |
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psram-tang-nano-9k
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Open HyperRAM interface for Nano 9K
I added a note about his to the controller's readme. "Quick discussion about going above 83Mhz".
Reading the GitHub code at https://github.com/zf3/psram-tang-nano-9k , I think it is missing the needed timing constraints for telling the timing analyser about the relationship between the PSRAM output data signals and the two clocks (shifted and unshifted).
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Gowin: PSRAM unusable on Tang Nano 9K: stuck in Wrapped Burst mode in read and write operations (HyperRAM on Tang Nano 4K works OK with Linear Bursts)
Another difference that I find in that W955D8MBYA data sheet compared to W955N8MBY, is that W955D8MBYA does not mention anywhere that differential signaling would be optional: but instead it marks it as required. If that is the case, then the question for Best Behavior(tm) of how to properly feed it LVDS does rise again. ( https://github.com/zf3/psram-tang-nano-9k/issues/1 )
Replied there, maybe they are looking at the same issue. I am also aware of the GitHub repo https://github.com/zf3/psram-tang-nano-9k that implements a PSRAM controller, but they don't do Bursted Transfers there.
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