riscv VS psram-tang-nano-9k

Compare riscv vs psram-tang-nano-9k and see what are their differences.


An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA (by zf3)
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riscv psram-tang-nano-9k
1 5
742 16
- -
1.0 4.1
over 1 year ago 5 months ago
Verilog Verilog
BSD 3-clause "New" or "Revised" License Apache License 2.0
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
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Posts with mentions or reviews of riscv. We have used some of these posts to build our list of alternatives and similar projects.

We haven't tracked posts mentioning riscv yet.
Tracking mentions began in Dec 2020.


Posts with mentions or reviews of psram-tang-nano-9k. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-10-10.
  • Open HyperRAM interface for Nano 9K
    2 projects | reddit.com/r/GowinFPGA | 10 Oct 2022
    I added a note about his to the controller's readme. "Quick discussion about going above 83Mhz".
    2 projects | reddit.com/r/GowinFPGA | 10 Oct 2022
    Reading the GitHub code at https://github.com/zf3/psram-tang-nano-9k , I think it is missing the needed timing constraints for telling the timing analyser about the relationship between the PSRAM output data signals and the two clocks (shifted and unshifted).
  • Gowin: PSRAM unusable on Tang Nano 9K: stuck in Wrapped Burst mode in read and write operations (HyperRAM on Tang Nano 4K works OK with Linear Bursts)
    2 projects | reddit.com/r/FPGA | 24 Sep 2022
    Another difference that I find in that W955D8MBYA data sheet compared to W955N8MBY, is that W955D8MBYA does not mention anywhere that differential signaling would be optional: but instead it marks it as required. If that is the case, then the question for Best Behavior(tm) of how to properly feed it LVDS does rise again. ( https://github.com/zf3/psram-tang-nano-9k/issues/1 )
    2 projects | reddit.com/r/FPGA | 24 Sep 2022
    Replied there, maybe they are looking at the same issue. I am also aware of the GitHub repo https://github.com/zf3/psram-tang-nano-9k that implements a PSRAM controller, but they don't do Bursted Transfers there.

What are some alternatives?

When comparing riscv and psram-tang-nano-9k you can also consider the following projects:

biriscv - 32-bit Superscalar RISC-V CPU

openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

zipcpu - A small, light weight, RISC CPU soft core

Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog

darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

uhd - The USRP™ Hardware Driver Repository

nano4k_hdmi_tx - Open-source HDMI/DVI transmitter for the Gowin GW1NSR-powered Tang Nano 4K

ice40_power - Power analysis of the ICE40UP5K-SG48 devices

riscv-cores-list - RISC-V Cores, SoC platforms and SoCs

serv - SERV - The SErial RISC-V CPU

cpu11 - Revengineered ancient PDP-11 CPUs, originals and clones