skywater-pdk
rocket-chip
skywater-pdk | rocket-chip | |
---|---|---|
27 | 12 | |
2,841 | 3,017 | |
1.0% | 1.2% | |
2.3 | 7.8 | |
8 months ago | 3 days ago | |
Python | Scala | |
Apache License 2.0 | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
skywater-pdk
-
Ask HN: Open-Source Simple CPU?
Preferably Intel compatible or able to run Linux? Something I can build in my garage or in a simple microprocessor fab.
https://github.com/google/skywater-pdk
-
Libre Silicon – Free semiconductors for everyone
It looks neat, but the process node is 1 um with 3 metal layers.
The open Skywater PDK is 130 nm : https://github.com/google/skywater-pdk (though I don't know how reliable the PDK is?)
-
Ask HN: How to start a fabless chip company targeting a modern process node?
From working in a somewhat related discipline, the PDKs for the high end nodes (think tsmc N16 and lower) are quite hard to obtain and require your org to pass security audit. In addition to that the cadence licenses are priced very much for a big-org rather than a startup.
Does your chip absolutely need a modern node? I'm assuming you've seen the open source skywater pdk, but here it is just in case. https://github.com/google/skywater-pdk
-
Cadence Genus&Innovus
If you need a free PDK, check out: https://github.com/google/skywater-pdk
-
DIY-Thermocam: The Affordable and Easy-to-Build Thermal Camera for Everyone
That would be really neat, but I haven't seen anyone even make a CMOS imager on SKY130.
https://github.com/google/skywater-pdk
One could make an array of thermopiles, like the hacker that made their own imager out of discrete diodes (digiOBSCURA) . But each pixel would cost $7.
https://www.digikey.com/en/products/detail/excelitas-technol...
One might be able to make an array of thermistors (possibly with active cooling using a peltier) like the diycamera (digiOBSCURA) below. Might be an application of combining many RC oscillators in a tree and recovering the signal with an FFT. I have a gut feeling this is possible, but haven't show it.
https://www.digikey.com/en/products/detail/panasonic-electro...
https://github.com/IdleHandsProject/diycamera (digiOBSCURA)
One could experiment with microbolometers on tinytapeout. https://elicit.org/search?q=cmos+microbolometer
https://tinytapeout.com/
-
Riscv board running quake II using a Radeon card.
Unlike x86_64 which can only legally be produced by two and one-quarter companies, RISC-V is a permissively open-sourced ISA so anyone can make a chip. Literally, you can download Verilog of Berkeley Rocket cores from Github and run it on an FPGA, or prep it to send to SkyWater to fab at 130nm.
- NCSU Free 45nmPDK
-
Making open source hardware design a reality
Taping out an actual chip inevitably involves IP that's not yours, e.g. the standard cell library and other 'physical' IP like memories and flash. You cannot open source that as it is not yours and in general the owners of it won't want to open source it either (though there are exceptions e.g. the Skywater 130nm PDK https://github.com/google/skywater-pdk).
In OpenTitan we've built all the 'logical' IP ourselves from the ground up. This is the Verilog RTL you can see in our repository but you need the 'physical' IP to make a real chip. We haven't built any physical IP so we need to get it from the traditional industry sources which means traditional industry licensing (i.e. very much not open).
- Cadence market share?
- Compiling Code into Silicon
rocket-chip
-
Recommendations for RISC-V on FPGA
Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?
-
RISC-V Pushes into the Mainstream
You could do a trial build of an in-order Rocket RISC-V core [1] to see how much space it takes up.
[1] https://github.com/chipsalliance/rocket-chip
- Can anyone explain simply how OpenSource the RISC-V actually is?
-
Stages of prototyping a RISC-V processor on an FPGA?
My definition of a RISC CPU is one that has a reduced instruction set. In other words, the category of CPU is defined by the size of the instruction set, not in how it is implemented. Consider for example RISC-V CPUs. These are defined by their open instruction set alone, in spite of the fact that many implementations of RISC-V CPUs exist: some pipelined, and some not.
- FPGA for RISC-V Processor
-
How are modern processors and their architecture designed?
More complex CPUs are typically completely out of scope for hand coding, therefore you can implement generators like: https://github.com/chipsalliance/rocket-chip
-
Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'"
We don't have Sifive's specifically but we do have the open source cores they've historically used to design their cores: https://github.com/riscv-boom/riscv-boom https://github.com/chipsalliance/rocket-chip
-
Project ideas for RISC-V?
This would allow you to experiment with your own chip or something like [the RocketChip generator](https://github.com/chipsalliance/rocket-chip).
-
Question: Does the 32bit version of Rocket still supports FPU
https://github.com/chipsalliance/rocket-chip/blob/c7da610430f51b02ebda37f3d444674dc8f2adbf/src/main/scala/system/Configs.scala#L28
-
The First Affordable RISC-V Computer Designed to Run Linux
I don't know about the u74 specifically, but sifive does seem to invest in a open source risc-v core called rocket-chip.
What are some alternatives?
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
RocksDB - A library that provides an embeddable, persistent key-value store for fast storage.
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
gssi - Stuff I worked on while at GSSI (L'Aquila, Italy)
quibble - Quibble - the custom Windows bootloader
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU
PeakRDL-uvm - Generate UVM register model from compiled SystemRDL input
Cores-VeeR-EH1 - VeeR EH1 core
Verilog.jl - Verilog for Julia
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development