simple-riscv
neo430
| simple-riscv | neo430 | |
|---|---|---|
| 5 | 3 | |
| 19 | 178 | |
| - | - | |
| 2.7 | 2.8 | |
| about 3 years ago | over 2 years ago | |
| VHDL | VHDL | |
| MIT License | BSD 3-clause "New" or "Revised" License |
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simple-riscv
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How to run DOOM on a custom-made CPU in VHDL
Have a look at https://github.com/hamsternz/simple-riscv/tree/main/sw for how I did this for my toy processor. In particular https://github.com/hamsternz/simple-riscv/tree/main/sw/image_to_mem does the heavy lifting.
- Running VIVADO project from batch- linux , by using tcl file.
- Looking for an rv32i asm program that covers all possible scenarios of all instructions for testing
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Is a single cycle CPU of any use besides learning?
If you want to see my ISA testing source have a look at: https://github.com/hamsternz/simple-riscv/blob/main/sw/asm/isa_test.S
neo430
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looking for 16 bit RISC ISA to implement on cyclon IV FPGA
If you insist on 16-bit you could check out the neo430
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Newbie needs help on retro-computer creation.
If you want a good example of a CISC style CPU converted to an FPGA look at the Neo430 it is based on the TI MSP430.
- The NEO430 Processor
What are some alternatives?
riscv-tests
serv - SERV - The SErial RISC-V CPU
riscv-formal - RISC-V Formal Verification Framework
fpga_torture - 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
rp32 - RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL
Cores-VeeR-EH1 - VeeR EH1 core
riscv-debug-dtm - 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
SoC - Github Repo for Embedded FPGA course by Vincent Claes
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
Arcade_Galaga - Galaga Arcade Core