neo430
fpga_torture
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| neo430 | fpga_torture | |
|---|---|---|
| 3 | 2 | |
| 178 | 25 | |
| - | - | |
| 2.8 | 0.0 | |
| over 2 years ago | over 1 year ago | |
| VHDL | VHDL | |
| BSD 3-clause "New" or "Revised" License | BSD 3-clause "New" or "Revised" License |
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neo430
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looking for 16 bit RISC ISA to implement on cyclon IV FPGA
If you insist on 16-bit you could check out the neo430
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Newbie needs help on retro-computer creation.
If you want a good example of a CISC style CPU converted to an FPGA look at the Neo430 it is based on the TI MSP430.
- The NEO430 Processor
fpga_torture
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Testing the FPGA board
For the second test you could use something like this: https://github.com/stnolting/fpga_torture
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Maximum FPGA resource utilization
FPGA-agnostic utilization / power-supply stress-test (VHDL): https://github.com/stnolting/fpga_torture
What are some alternatives?
serv - SERV - The SErial RISC-V CPU
sidechan - Side channel communication test within an FPGA
forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
riscv-debug-dtm - 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
SoC - Github Repo for Embedded FPGA course by Vincent Claes
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
fpga-fft - A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm