neo430
forth-cpu
| neo430 | forth-cpu | |
|---|---|---|
| 3 | 2 | |
| 178 | 315 | |
| - | - | |
| 2.8 | 2.6 | |
| over 2 years ago | about 2 years ago | |
| VHDL | VHDL | |
| BSD 3-clause "New" or "Revised" License | - |
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neo430
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looking for 16 bit RISC ISA to implement on cyclon IV FPGA
If you insist on 16-bit you could check out the neo430
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Newbie needs help on retro-computer creation.
If you want a good example of a CISC style CPU converted to an FPGA look at the Neo430 it is based on the TI MSP430.
- The NEO430 Processor
forth-cpu
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Designs targeting specific boards?
Like in my head I thought having a piece of verilog and having enough LUTs in any board would do the thing, so what meant here? An example https://github.com/howerj/forth-cpu mentions that the target board is a specific Xilinx.
- Forth SoC Written in VHDL
What are some alternatives?
serv - SERV - The SErial RISC-V CPU
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
fpga_torture - 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
riscv-debug-dtm - 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
fpga-toolchain - Multi-platform nightly builds of open source FPGA tools
neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
sdram-fpga - A FPGA core for a simple SDRAM controller.
SoC - Github Repo for Embedded FPGA course by Vincent Claes
fpga-fft - A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
VHDL-Guide - VHDL Guide