neo430
SoC
neo430 | SoC | |
---|---|---|
3 | 1 | |
178 | 11 | |
- | - | |
2.8 | 1.1 | |
over 2 years ago | about 1 year ago | |
VHDL | VHDL | |
BSD 3-clause "New" or "Revised" License | - |
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neo430
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looking for 16 bit RISC ISA to implement on cyclon IV FPGA
If you insist on 16-bit you could check out the neo430
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Newbie needs help on retro-computer creation.
If you want a good example of a CISC style CPU converted to an FPGA look at the Neo430 it is based on the TI MSP430.
- The NEO430 Processor
SoC
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I2C communication between Minized to arduino
You can have a look at this : https://github.com/cteqeu/Embedded-FPGA/tree/master/MiniZED/eFPGA_I2C_PS
What are some alternatives?
serv - SERV - The SErial RISC-V CPU
Vitis_Accel_Examples - Vitis_Accel_Examples
fpga_torture - 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
kvm-ip-zynq - KVM over IP Gateway targeting Zynq-7000 SoC
forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL
red-pitaya-notes - Notes on the Red Pitaya Open Source Instrument
riscv-debug-dtm - 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
fpga-fft - A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog