neo430
riscv-debug-dtm
Our great sponsors
neo430 | riscv-debug-dtm | |
---|---|---|
3 | 3 | |
178 | 12 | |
- | - | |
2.8 | 0.0 | |
over 2 years ago | over 1 year ago | |
VHDL | VHDL | |
BSD 3-clause "New" or "Revised" License | BSD 3-clause "New" or "Revised" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
neo430
-
looking for 16 bit RISC ISA to implement on cyclon IV FPGA
If you insist on 16-bit you could check out the neo430
-
Newbie needs help on retro-computer creation.
If you want a good example of a CISC style CPU converted to an FPGA look at the Neo430 it is based on the TI MSP430.
- The NEO430 Processor
riscv-debug-dtm
-
Input to FPGA
Here is a link to a JTAG Transport Module and some instructions how to read/write data words using OpenOCD: https://github.com/stnolting/riscv-debug-dtm
-
Looking for feedback on my most recent project (anything welcome)
just a brief readme: https://github.com/stnolting/riscv-debug-dtm
- Confused about the JTAG interface
What are some alternatives?
serv - SERV - The SErial RISC-V CPU
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
fpga_torture - π₯ Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
wb_spi_bridge - π A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).
forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL
neorv32-riscof - βοΈPort of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
SoC - Github Repo for Embedded FPGA course by Vincent Claes
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
neoTRNG - π² A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
simple-riscv - A simple three-stage RISC-V CPU
Arcade_Galaga - Galaga Arcade Core