neo430
neoTRNG
| neo430 | neoTRNG | |
|---|---|---|
| 3 | 10 | |
| 178 | 152 | |
| - | - | |
| 2.8 | 7.5 | |
| over 2 years ago | 28 days ago | |
| VHDL | VHDL | |
| BSD 3-clause "New" or "Revised" License | BSD 3-clause "New" or "Revised" License |
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neo430
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looking for 16 bit RISC ISA to implement on cyclon IV FPGA
If you insist on 16-bit you could check out the neo430
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Newbie needs help on retro-computer creation.
If you want a good example of a CISC style CPU converted to an FPGA look at the Neo430 it is based on the TI MSP430.
- The NEO430 Processor
neoTRNG
- A really tiny and platform-independent true random number generator for FPGAs and ASICs
- Show HN: A tiny and platform-agnostic true random number generator for FPGA/ASIC
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Synthesizable LFSR counter (feedback 16,13)
This TRNG (VHDL) provides some kind of "imulation mode where the entropy source is replaced by a LFSR. When simulated, the testbench prints the random data to the simulator console. Maybe this can help as starting point.
- A tiny and platform-agnostic TRUE random number generator for any FPGA
- A Tiny and Platform-Agnostic True Random Number Generator for Any FPGA
- Show HN: A Tiny and Platform-Agnostic True Random Number Generator for Any FPGA
- A Tiny and Platform-Independent True Random Number Generator for any FPGA.
What are some alternatives?
serv - SERV - The SErial RISC-V CPU
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
fpga_torture - 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL
neorv32-setups - 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
riscv-debug-dtm - 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
neorv32-riscof - ✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
SoC - Github Repo for Embedded FPGA course by Vincent Claes
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
simple-riscv - A simple three-stage RISC-V CPU
Arcade_Galaga - Galaga Arcade Core