neo430
Arcade_Galaga
| neo430 | Arcade_Galaga | |
|---|---|---|
| 3 | 1 | |
| 178 | 8 | |
| - | - | |
| 2.8 | 5.5 | |
| over 2 years ago | 9 months ago | |
| VHDL | VHDL | |
| BSD 3-clause "New" or "Revised" License | - |
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neo430
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looking for 16 bit RISC ISA to implement on cyclon IV FPGA
If you insist on 16-bit you could check out the neo430
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Newbie needs help on retro-computer creation.
If you want a good example of a CISC style CPU converted to an FPGA look at the Neo430 it is based on the TI MSP430.
- The NEO430 Processor
Arcade_Galaga
What are some alternatives?
serv - SERV - The SErial RISC-V CPU
Hastlayer-SDK - Turning .NET software into FPGA hardware for faster execution and lower power usage.
fpga_torture - 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
w11 - PDP-11/70 CPU core and SoC
forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
riscv-debug-dtm - 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
SoC - Github Repo for Embedded FPGA course by Vincent Claes
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.