rocket-chip VS wd65c02

Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?

You could do a trial build of an in-order Rocket RISC-V core [1] to see how much space it takes up.

[1] https://github.com/chipsalliance/rocket-chip

My definition of a RISC CPU is one that has a reduced instruction set. In other words, the category of CPU is defined by the size of the instruction set, not in how it is implemented. Consider for example RISC-V CPUs. These are defined by their open instruction set alone, in spite of the fact that many implementations of RISC-V CPUs exist: some pipelined, and some not.

More complex CPUs are typically completely out of scope for hand coding, therefore you can implement generators like: https://github.com/chipsalliance/rocket-chip

We don't have Sifive's specifically but we do have the open source cores they've historically used to design their cores: https://github.com/riscv-boom/riscv-boom https://github.com/chipsalliance/rocket-chip

This would allow you to experiment with your own chip or something like [the RocketChip generator](https://github.com/chipsalliance/rocket-chip).

https://github.com/chipsalliance/rocket-chip/blob/c7da610430f51b02ebda37f3d444674dc8f2adbf/src/main/scala/system/Configs.scala#L28

I don't know about the u74 specifically, but sifive does seem to invest in a open source risc-v core called rocket-chip.

I'm implementing a 6502. I wrote a test-bench program in Verilog that takes a mem file for the test program, and another for the test-plan, and verifies the CPU's execution against the test plan. You can check it out. Feel free to steal ideas. You can even use the code itself, so long as you honor the GPL it's under. Here is a link to the actual file inside the project.

I started such a project in VeriLog once, if you want a reference. I abandoned it before getting to branches, however, in favor of writing a 6502 implementation.

You can look for ideas at my test bench. The testbench is available here. Don't copy any actual code unless you are willing to abide by the GPL, though. I doubt it will help you in the literal way, anyways, as it is built for testing a CISC CPU, so some adaptations will be required no matter how free you are to use the code. I am hoping it will give you some ideas.

I have a design (available here) that has loops in the timing report after implementation. The problem is that I cannot seem to trace the nets I'm seeing in the report to my code, and those I did manage to trace seem to be routed through non-blocking assignments. I'm missing something, but I'm not sure what.

The project source is here.

So I went through all the files in the wd65c02/wd65c02.srcs/sources_1/new/ directory, but I can't find the code snippets that you're talking about?