riscv-debug-dtm
neo430
| riscv-debug-dtm | neo430 | |
|---|---|---|
| 3 | 3 | |
| 12 | 178 | |
| - | - | |
| 0.0 | 2.8 | |
| over 1 year ago | over 2 years ago | |
| VHDL | VHDL | |
| BSD 3-clause "New" or "Revised" License | BSD 3-clause "New" or "Revised" License |
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riscv-debug-dtm
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Input to FPGA
Here is a link to a JTAG Transport Module and some instructions how to read/write data words using OpenOCD: https://github.com/stnolting/riscv-debug-dtm
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Looking for feedback on my most recent project (anything welcome)
just a brief readme: https://github.com/stnolting/riscv-debug-dtm
- Confused about the JTAG interface
neo430
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looking for 16 bit RISC ISA to implement on cyclon IV FPGA
If you insist on 16-bit you could check out the neo430
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Newbie needs help on retro-computer creation.
If you want a good example of a CISC style CPU converted to an FPGA look at the Neo430 it is based on the TI MSP430.
- The NEO430 Processor
What are some alternatives?
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
serv - SERV - The SErial RISC-V CPU
wb_spi_bridge - 🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).
fpga_torture - 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
neorv32-riscof - ✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL
neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
SoC - Github Repo for Embedded FPGA course by Vincent Claes
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
simple-riscv - A simple three-stage RISC-V CPU
Arcade_Galaga - Galaga Arcade Core