quasiSoC
spu32
| quasiSoC | spu32 | |
|---|---|---|
| 1 | 1 | |
| 91 | 60 | |
| - | - | |
| 6.4 | 0.0 | |
| 10 days ago | almost 2 years ago | |
| C | C | |
| GNU General Public License v3.0 only | MIT License |
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quasiSoC
spu32
-
Designing instruction decoder
You asked for "elegant and simple". Disregarding your request, here's how I decode RISC-V: https://github.com/maikmerten/spu32/blob/master/cpu/decoder.v
What are some alternatives?
Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog
shecc - A self-hosting and educational C optimizing compiler
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
RISCV - A Pipelined RISC-V RV32I Core in Verilog [Moved to: https://github.com/georgeyhere/Toast-RV32i]
RVVM - The RISC-V Virtual Machine
esp - Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
rt-thread - RT-Thread is an open source IoT real-time operating system (RTOS).
cariboulite - CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
SAP1 - RTL Implementation of Malvino's SAP1. I was inspired to do this after seeing Ben Eater's Breadboard implementation