pymtl3
SpinalHDL
pymtl3 | SpinalHDL | |
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5 | 8 | |
350 | 1,523 | |
2.3% | 2.0% | |
4.6 | 9.8 | |
7 days ago | 8 days ago | |
Python | Scala | |
BSD 3-clause "New" or "Revised" License | GNU General Public License v3.0 or later |
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pymtl3
- Firrtl – Flexible Intermediate Representation for RTL
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Why are there only 3 languages for FPGA development?
Also PyMTL, PyRTL, and MyHDL.
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Choice of Python HDL library
PyMTL
- RISC-V reference model in Python
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Tools for designing hardware in Python
Any hardware designers here who use Python for designing hardware? There are a bunch of libraries that all seem promising MyHDL, PyRTL, PyVerilog, PyLog, PyMTL3, ... All seem to work roughly the same. Write code in Python and transpile it to VHDL/Verilog. Which of these are popular and well-maintained? MyHDL looks good but it's last release was 0.10 in 2018 and for hardware design you don't want to rely on 0.x software. Anything like Chisel for Python.
SpinalHDL
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1800-2023 – IEEE Standard for SystemVerilog
I'd love to see textual preprocessors kinda banned. Or at least done upstream and outside of the language. You can't both be and also have a textual preprocessor defined internally. It doesn't work.
I really like what Zig and C++ are doing with `const`.
https://ikrima.dev/dev-notes/zig/zig-metaprogramming/
Have you looked at Spinal?
https://github.com/SpinalHDL/SpinalHDL
https://spinalhdl.github.io/SpinalDoc-RTD/master/index.html
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Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system
Many companies do just write entire modern SoCs in straight Verilog (maybe with some autogenerated Verilog hacked in there) with no other major organization tools aside from the typical project management stuff. The load-store unit of a modern CPU alone easily exceeds 10k lines of Verilog. It's a similar thing as people who work with kernels—after all, the page table management code in a modern operating system like Linux is absolutely monstrous but still people are able to understand it well enough to be able to make the changes they need and get out.
If you are interested in other languages which hope to make this sort of stuff easier, I'd recommend taking a look at design productivity languages like Chisel and it's associated Chipyard [1], SpinalHDL [2], and Bluespec [3]. Each of these are meant to make defining extremely complex hardware more manageable for humans and there's a lot of interesting work going on right now with each of them.
[1] https://github.com/ucb-bar/chipyard
[2] https://github.com/SpinalHDL/SpinalHDL
[3] https://github.com/B-Lang-org/bsc
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Simple skid buffer implementation
I have just found that SpinalHDL also implemented two halves of the fully registered buffer in Stream.scala.
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Why are there only 3 languages for FPGA development?
Don’t forget SpinalHDL that was forked off of Chisel 2 I believe. These DSLs really leveraged the software features of Scala to help build generalised/modular systems. And are generally a quality of life improvement in the language features available.
- SpinalHDL – A high level hardware description language based on Scala
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Share some github FPGA projects (bonus if they include C++, Python, or other files)
A lot of reuse from other FOSH projects, including Litex, SpinalHDL, betrusted & u/alexforencich verilog-wishbone. Thanks to all of them :-)
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Suggest advance project ideas
You could try to implement a PCIe root complex for FOSS SoCs, connecting to e.g. Wishbone as the main bus. There's already some DDR3 controller (or this one) and USB Host controller out there, and even device-side PCIe, but no FOSS host-side PCIe that I know of. Probably quite a difficult job though, even sticking to the lower-speed PCIe 1.
- Chisel/Firrtl Hardware Compiler Framework
What are some alternatives?
myhdl - The MyHDL development repository
chisel - Chisel: A Modern Hardware Design Language
PyRTL - A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extendability rather than performance or optimization is the overarching goal.
amaranth - A modern hardware definition language and toolchain based on Python
Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL
litex - Build your hardware, easily!
hVHDL_example_project - An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has build scripts for most common FPGAs
chiselverify - A dynamic verification library for Chisel.
hVHDL_fixed_point - VHDL library of high abstraction level synthesizable mathematical functions for multiplication, division and sin/cos functionalities and abc to dq transforms.
litepcie - Small footprint and configurable PCIe core
migen - A Python toolbox for building complex digital hardware
circt - Circuit IR Compilers and Tools