nmigen
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen (by m-labs)
pyverilator
Python wrapper for verilator model (by csail-csg)
nmigen | pyverilator | |
---|---|---|
3 | 1 | |
643 | 70 | |
1.2% | - | |
1.8 | 0.0 | |
over 2 years ago | 3 months ago | |
Python | Python | |
GNU General Public License v3.0 or later | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
nmigen
Posts with mentions or reviews of nmigen.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-06-07.
-
Help a newbie
You can either decide to learn VHDL/Verilog, or use something like nmigen. I recommend learning either Verilog or VHDL anyway, so you can at least read and understand existing designs, but I personally use nmigen.
-
Do these work as JTAG programmers?
Alternatively, you can just use Vivado to build the bitstream and then use alternative tools like https://github.com/trabucayre/openFPGALoader and http://xc3sprog.sourceforge.net/ to upload the bitstream to your FPGA. This is what I do since I use nmigen myself.
- How to compare HDL simulation/implementation results to Matlab?
pyverilator
Posts with mentions or reviews of pyverilator.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-06-01.
-
How to compare HDL simulation/implementation results to Matlab?
I'd use something I could drive from Python, like https://github.com/csail-csg/pyverilator and verilator since it is fast. I'd containerize the tests and use [py.test]https://docs.pytest.org/en/6.2.x/) to run specific unit or integration tests. Ideally everything would be parameterized.
What are some alternatives?
When comparing nmigen and pyverilator you can also consider the following projects:
myhdl - The MyHDL development repository
Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL
qemu - Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.
openFPGALoader - Universal utility for programming FPGA
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
XVC-FTDI-JTAG - Xilinx virtual cable server for generic FTDI 4232H.
xvcd - Xilinx Virtual Cable Daemon
conifer - Collect and revisit web pages.