microwatt VS rocket-chip

My favorite part of this project is the pretty large battery of test cases. A lot of chip rtl releases don't bother with open sourcing the verification too, and that's arguably more useful than the rtl in the first place.

https://github.com/antonblanchard/microwatt/tree/master/test...

MicroWatt is the only one I know of.

https://github.com/antonblanchard/microwatt

I have several OpenPOWER systems, including the POWER9 I use as my usual desktop. Besides IBM and other server manufacturers like Tyan and Wistron, you can get them as Raptor workstations and servers.

If you want an OpenPOWER design to play with, look at Microwatt ( https://github.com/antonblanchard/microwatt ) which is complete enough to boot Linux.

Not true, as of 2019 the power ISA is able to be used without needing to pay any royalties to ibm under the openpower foundation. There's already a few projects that have taken advantage of it such as libreSOC and Microwatt. Source code for various firmware components are also freely available pertaining to the power platform.

https://github.com/antonblanchard/microwatt is an example of a Linux-capable 64-bit core that has been submitted on multiple Open MPW shuttles:

GitHub https://github.com/openpower-cores https://github.com/antonblanchard/microwatt

At the other end of the scale, if anyone wants to play you can run a little openpower CPU on a FPGA with completely open source. https://github.com/antonblanchard/microwatt

It's capable of running Linux, some example docs are https://shenki.github.io/boot-linux-on-microwatt/

Why dismiss POWER or SPARC ? :-)

Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?

You could do a trial build of an in-order Rocket RISC-V core [1] to see how much space it takes up.

[1] https://github.com/chipsalliance/rocket-chip

My definition of a RISC CPU is one that has a reduced instruction set. In other words, the category of CPU is defined by the size of the instruction set, not in how it is implemented. Consider for example RISC-V CPUs. These are defined by their open instruction set alone, in spite of the fact that many implementations of RISC-V CPUs exist: some pipelined, and some not.

More complex CPUs are typically completely out of scope for hand coding, therefore you can implement generators like: https://github.com/chipsalliance/rocket-chip

We don't have Sifive's specifically but we do have the open source cores they've historically used to design their cores: https://github.com/riscv-boom/riscv-boom https://github.com/chipsalliance/rocket-chip

This would allow you to experiment with your own chip or something like [the RocketChip generator](https://github.com/chipsalliance/rocket-chip).

https://github.com/chipsalliance/rocket-chip/blob/c7da610430f51b02ebda37f3d444674dc8f2adbf/src/main/scala/system/Configs.scala#L28

I don't know about the u74 specifically, but sifive does seem to invest in a open source risc-v core called rocket-chip.