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Verilog openpower Projects
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a2o
The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue. It is now being updated for compliancy and integration into open projects. (by OpenPOWERFoundation)
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WorkOS
The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.
Project mention: Microwatt: A tiny Open POWER ISA softcore written in VHDL 2008 | /r/patient_hackernews | 2023-10-23
NOTE:
The open source projects on this list are ordered by number of github stars.
The number of mentions indicates repo mentiontions in the last 12 Months or
since we started tracking (Dec 2020).
Verilog openpower related posts
- Microwatt: A tiny Open POWER ISA softcore written in VHDL 2008
- Microwatt: A tiny Open POWER ISA softcore written in VHDL 2008
- Arm wants to charge dramatically more for chip licenses
- How long until RISC gets adopted for the desktop?
- Build Open Silicon with Google
- Any raw binary generic platform-agnostic test roms for PowerPC?
- What would you think if the Amiga line jumped from PowerPc to RISC-V CPUs?
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