hdl_checker
vcdvcd
| hdl_checker | vcdvcd | |
|---|---|---|
| 4 | 1 | |
| 183 | 49 | |
| - | - | |
| 0.0 | 5.9 | |
| 5 months ago | 3 months ago | |
| Python | Python | |
| GNU General Public License v3.0 only | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
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hdl_checker
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Any better options than Sigasi?
I've written a LSP that uses modelsim, ghdl or Vivado to do error checking: https://github.com/suoto/hdl_checker
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What Editor is Everyone Using for FPGA design? (2021)
NeoVim + CoC + hdl_checker
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VHDL native lsp
As others mentioned, rust_hdl and ghdl ls are worth checking out. If your project has both VHDL and Verilog/SystemVerilog, might be worth checking https://github.com/suoto/hdl_checker (disclaimer, I'm the author). It's got less LS features than the other two but if you use it with modelsim it'll provide mixed language syntax check.
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IDE / Editor of choice
Specifically for HDL-files a lot of progress has been made in the last couple of years on lsp-mode and external LSP servers for code analysis of both VHDL and SystemVerilog. For SV I use the https://github.com/suoto/hdl_checker server that passes the code you are working on live to the Linting engine in Questa/ModelSim and marks the warning lines in the editor. It's nice to get immediate feedback on missing semicolons etc. although it still has a hard time handling large projects.
vcdvcd
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Running CLI packages
I want to run this package from Spyder IDE (or Jupyter Notebook) on my Anaconda installation. I can install the package from PyPI just fine. However, from the documentation it is designed to be run from CLI. So, when given the command "vcdcat x.vcd" it should dump the contents to the command line. I tried writing this command in Anaconda prompt
What are some alternatives?
completor.vim - Async completion framework made ease.
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
rust_hdl
cocotb-bus - Pre-packaged testbenching tools and reusable bus interfaces for cocotb
veridian - A SystemVerilog Language Server
PlatformIO - Your Gateway to Embedded Software Development Excellence :alien:
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
pymtl3 - Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
edalize - An abstraction library for interfacing EDA tools