hdl_checker
| hdl_checker | ffi-navigator | |
|---|---|---|
| 4 | 1 | |
| 183 | 223 | |
| - | - | |
| 0.0 | 1.8 | |
| 5 months ago | about 1 year ago | |
| Python | Python | |
| GNU General Public License v3.0 only | Apache License 2.0 |
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hdl_checker
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Any better options than Sigasi?
I've written a LSP that uses modelsim, ghdl or Vivado to do error checking: https://github.com/suoto/hdl_checker
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What Editor is Everyone Using for FPGA design? (2021)
NeoVim + CoC + hdl_checker
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VHDL native lsp
As others mentioned, rust_hdl and ghdl ls are worth checking out. If your project has both VHDL and Verilog/SystemVerilog, might be worth checking https://github.com/suoto/hdl_checker (disclaimer, I'm the author). It's got less LS features than the other two but if you use it with modelsim it'll provide mixed language syntax check.
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IDE / Editor of choice
Specifically for HDL-files a lot of progress has been made in the last couple of years on lsp-mode and external LSP servers for code analysis of both VHDL and SystemVerilog. For SV I use the https://github.com/suoto/hdl_checker server that passes the code you are working on live to the Linting engine in Questa/ModelSim and marks the warning lines in the editor. It's nice to get immediate feedback on missing semicolons etc. although it still has a hard time handling large projects.
ffi-navigator
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Install FFI Navigator as LSP in Lazy.nvim
I would like to install https://github.com/tqchen/ffi-navigator. It seems to come as a LSP but isn't supported by Mason and I am not sure how to set it up in Lazy.nvim.
What are some alternatives?
completor.vim - Async completion framework made ease.
nebuly - The user analytics platform for LLMs
rust_hdl
tvm - Open deep learning compiler stack for cpu, gpu and specialized accelerators
veridian - A SystemVerilog Language Server
anakin-language-server - Yet another Jedi Python language server
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
mlc-llm - Enable everyone to develop, optimize and deploy AI models natively on everyone's devices.
teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
pylance-release - Documentation and issues for Pylance
vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
edalize - An abstraction library for interfacing EDA tools