go-hdl
Hdl is a tool for easing the work with hardware description languages. (by m-kru)
riscv
RISC-V CPU Core (RV32IM) (by ultraembedded)
go-hdl | riscv | |
---|---|---|
2 | 2 | |
12 | 1,040 | |
- | - | |
0.0 | 1.8 | |
over 1 year ago | over 2 years ago | |
Go | Verilog | |
GNU General Public License v3.0 only | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
go-hdl
Posts with mentions or reviews of go-hdl.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-05-11.
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Code Checking for VHDL
I personally use 2 tools. The first one catches syntax errors, the second one can catch some logical errors. ghdl, thdl. The commands are respectively ghdl -s --std=08 path/to/file, thdl vet.
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Thdl - tool for easing the work with hardware description languages.
I have implemented the tool that some might find interesting https://github.com/m-kru/go-thdl. It is very similar in its concept to go. It allows vetting the code, seeing the documentation and generating the code (not yet supported). It uses simplified syntactic analysis, however it handles for example OSVVM and UVVM without any errors. Thanks to the simplified analysis the response is instant from human point of view. Currently only VHDL is supported, as this is my daily language, but adding support for example for SystemVerilog is foreseen.
riscv
Posts with mentions or reviews of riscv.
We have used some of these posts to build our list of alternatives
and similar projects.
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Ultraembedded RISCV Module
I have been trying to execute some instructions to the ultraembedded riscv module https://github.com/ultraembedded/riscv
- I made my own silicon chip: Project Silicon Rider