fusesoc
satcat5
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| fusesoc | satcat5 | |
|---|---|---|
| 12 | 25 | |
| 1,118 | 387 | |
| - | 36.7% | |
| 7.3 | 3.8 | |
| 18 days ago | 2 months ago | |
| Python | VHDL | |
| BSD 2-clause "Simplified" License | CERN Open Hardware Licence Version 2 - Weakly Reciprocal |
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
fusesoc
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fusesoc VS vextproj - a user suggested alternative
2 projects | 28 Mar 2024
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Introduction to FPGAs
Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
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CI/CD for FPGA builds
Check out FuseSoC: https://github.com/olofk/fusesoc it can run Vivado builds for you (as well as many other tools). It may be less work to get FuseSoC setup then work out a CLI Vivado batch flow from scratch.
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Besides misterFPGA what else can I play with on a DE10-nano?
Also, the FuseSOC and LiteX projects both support the DE10 nano, and can be used to roll your own custom SOCs with RISC-V or OpenRISC cores.
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Why isn't all verification work done in Python
Integration with the dependency and build tool I use (FuseSoc) is clumsy.
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Using Python with Vivado Projects
The "fusesoc" project may be of interest to you.
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Any recommendations for an RTL "standard library"?
FuseSoC is an RTL package manager. It will automatically download the latest versions of required components when you build. It also comes with a bunch of great options for components here:
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What should a modern IP library look like?
Have to correct this slightly: I just heard of my first HDL package manager in this thread. FuseSOC: https://github.com/olofk/fusesoc - Thanks u/gac_cag!
- Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
- Industry development process?
satcat5
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Layout of Rust's u128 and i128 changed
I needed 128-bit and 256-bit integers on an embedded project recently.
In short, it was for fixed-point digital signal processing. The raw input and output samples were int64_t. We needed to add, subtract, multiply, and accumulate these to do filtering and linear regression with no loss of precision.
Conventional bigintegers weren't an option because the target application doesn't allow heap allocation. So we rolled our own [1] stack-allocated, fixed-width big integer class.
[1] https://github.com/the-aerospace-corporation/satcat5/blob/ma...
- Show HN: SatCat5, the open-source FPGA Ethernet switch
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CRC32 algorithm match value between 96 bit wide data bus and 24 bit wide data bus
And here's an open-source implementation I wrote a few years back. You can skip the part at the end that handles variable-length trailing bytes, since you have a fixed-width input.
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Questions about lattice ecp5 fpga.
My SatCat5 project also has a few options. Anything under src/vhdl/common/cfgbus_* can be connected to AXI or Wishbone with a simple adapter.
- SatCat5: FPGA gateware that implements a low-power, mixed-media Ethernet switch
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GPSDO without VCXO?
For an all-digital solution, here's an NCO that generates an arbitrary-frequency square wave from a numeric counter.
- network switch
What are some alternatives?
litex - Build your hardware, easily!
verilog-ethernet - Verilog Ethernet components for FPGA implementation
edalize - An abstraction library for interfacing EDA tools
SpinalHDL - Scala based HDL
opentitan - OpenTitan: Open source silicon root of trust
surf - A huge VHDL library for FPGA development
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)
teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
rocket-chip - Rocket Chip Generator
chisel - Chisel: A Modern Hardware Design Language