freepdk-45nm
edalize
| freepdk-45nm | edalize | |
|---|---|---|
| 1 | 4 | |
| 108 | 592 | |
| 0.0% | - | |
| 10.0 | 7.2 | |
| about 4 years ago | 9 days ago | |
| Verilog | Python | |
| - | BSD 2-clause "Simplified" License |
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freepdk-45nm
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Compiling Code into Silicon
Pretty neat, a python tool that converts Verilog to an IC layout so that you can make your own custom SOC (assuming you have a substantial budget to pay for fab).
Since it's not clearly stated on the front page, I had to go digging to figure out what processes it supports. Looks like FreePDK45, which is "an open-source generic process design kit (PDK) (i.e., does not correspond to any real process and cannot be fabricated)" [0], ASAP7 "Warning Work in progress (not ready for use)" [1] and Skywater130 which "As of May 2020, this repository is targeting the SKY130 process node. If the SKY130 process node release is successful then in the future more advanced technology nodes may become available." [2] The floorplanner supports their ZeroSOC [3] which I guess is based on TitanSOC [4]
If this sounds negative, it's not, I just couldn't figure out what processes this was intended for without digging. ASAP7 is Arm and NCSU, and Skywater130 is Skywater and Google.
[0] https://github.com/mflowgen/freepdk-45nm
edalize
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Dropping EDA-GUI's 101
Check out FuseSoC: https://github.com/olofk/fusesoc which can handle Vivado builds for you (utilizing edalize: https://github.com/olofk/edalize) along with some nice package management. It can run against multiple tools so you can also get it to build simulations using Verilator or a commercial EDA tool if you have access to them.
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Introduction to FPGAs
Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
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Compiling Code into Silicon
This reminds me very much of edalize[1], which does something very similar.
[1]: https://github.com/olofk/edalize
- Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
What are some alternatives?
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
Verilog.jl - Verilog for Julia
apio - :seedling: Open source ecosystem for open FPGA boards
opentitan - OpenTitan: Open source silicon root of trust
icestudio - :snowflake: Visual editor for open FPGA boards
chisel - Chisel: A Modern Hardware Design Language
rggen - Code generation tool for control and status registers
zerosoc - Demo SoC for SiliconCompiler.
sphinx-vhdl