freepdk-45nm VS Verilog.jl

Pretty neat, a python tool that converts Verilog to an IC layout so that you can make your own custom SOC (assuming you have a substantial budget to pay for fab).

Since it's not clearly stated on the front page, I had to go digging to figure out what processes it supports. Looks like FreePDK45, which is "an open-source generic process design kit (PDK) (i.e., does not correspond to any real process and cannot be fabricated)" [0], ASAP7 "Warning Work in progress (not ready for use)" [1] and Skywater130 which "As of May 2020, this repository is targeting the SKY130 process node. If the SKY130 process node release is successful then in the future more advanced technology nodes may become available." [2] The floorplanner supports their ZeroSOC [3] which I guess is based on TitanSOC [4]

If this sounds negative, it's not, I just couldn't figure out what processes this was intended for without digging. ASAP7 is Arm and NCSU, and Skywater130 is Skywater and Google.

[0] https://github.com/mflowgen/freepdk-45nm

It doesn't have to be. I once made a julia->verilog transpiler that even recompiled your julia functions with verilator, so you could verify that the code was correct.

https://github.com/interplanetary-robot/Verilog.jl

Of course, gaining traction on something like this is tricky.

I actually think Erlang/BEAM would be a great choice for making EDA tools, because it has concurrent execution model that you could probably very easily make play nice in rudimentary simulations of circuits that have triggers (`always @` sort of stuff.

A long long long time ago, I wrote this (currently very unmaintained) julia project, don't know if this is useful to you, but it's pretty clear that there is a LOT of potential for julia in this domain: https://github.com/interplanetary-robot/Verilog.jl