edalize
Verilog.jl
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| edalize | Verilog.jl | |
|---|---|---|
| 4 | 2 | |
| 590 | 46 | |
| - | - | |
| 7.3 | 0.0 | |
| 9 days ago | about 7 years ago | |
| Python | Julia | |
| BSD 2-clause "Simplified" License | GNU General Public License v3.0 or later |
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edalize
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Dropping EDA-GUI's 101
Check out FuseSoC: https://github.com/olofk/fusesoc which can handle Vivado builds for you (utilizing edalize: https://github.com/olofk/edalize) along with some nice package management. It can run against multiple tools so you can also get it to build simulations using Verilator or a commercial EDA tool if you have access to them.
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Introduction to FPGAs
Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
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Compiling Code into Silicon
This reminds me very much of edalize[1], which does something very similar.
[1]: https://github.com/olofk/edalize
- Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
Verilog.jl
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Compiling Code into Silicon
It doesn't have to be. I once made a julia->verilog transpiler that even recompiled your julia functions with verilator, so you could verify that the code was correct.
https://github.com/interplanetary-robot/Verilog.jl
Of course, gaining traction on something like this is tricky.
I actually think Erlang/BEAM would be a great choice for making EDA tools, because it has concurrent execution model that you could probably very easily make play nice in rudimentary simulations of circuits that have triggers (`always @` sort of stuff.
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Julia Receives DARPA Award to Accelerate Electronics Simulation by 1,000x
A long long long time ago, I wrote this (currently very unmaintained) julia project, don't know if this is useful to you, but it's pretty clear that there is a LOT of potential for julia in this domain: https://github.com/interplanetary-robot/Verilog.jl
What are some alternatives?
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
Octavian.jl - Multi-threaded BLAS-like library that provides pure Julia matrix multiplication
freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
apio - :seedling: Open source ecosystem for open FPGA boards
svls - SystemVerilog language server
icestudio - :snowflake: Visual editor for open FPGA boards
Modia.jl - Modeling and simulation of multidomain engineering systems
rggen - Code generation tool for control and status registers
Automa.jl - A julia code generator for regular expressions