core-v-cores VS scr1

Compare core-v-cores vs scr1 and see what are their differences.

core-v-cores

CORE-V Family of RISC-V Cores (by openhwgroup)

scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog (by syntacore)
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core-v-cores scr1
1 2
174 775
6.3% 3.2%
5.2 3.0
2 months ago 19 days ago
SystemVerilog
- GNU General Public License v3.0 or later
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

core-v-cores

Posts with mentions or reviews of core-v-cores. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-07-04.

scr1

Posts with mentions or reviews of scr1. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-07-04.

What are some alternatives?

When comparing core-v-cores and scr1 you can also consider the following projects:

VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation

riscv-simple-sv - A simple RISC V core for teaching

M2GL025-Creative-Board - Igloo2 M2GL025 Creative Development Board

FPGA-Video-Processing - Realtime video processing w/ Gaussian + Sobel Filters targeting Artix-7 FPGA

ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

friscv - RISCV CPU implementation in SystemVerilog

clic - RISC-V fast interrupt controller

Cores-VeeR-EL2 - VeeR EL2 Core

Cores-VeeR-EH1 - VeeR EH1 core

darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!