chisel-template
Chisel HDL Template Repository (by carlosedp)
rocket-chip
Rocket Chip Generator (by chipsalliance)
| chisel-template | rocket-chip | |
|---|---|---|
| 1 | 12 | |
| 4 | 3,017 | |
| - | 1.2% | |
| 10.0 | 7.8 | |
| about 1 year ago | 3 days ago | |
| Scala | Scala | |
| BSD 3-clause "New" or "Revised" License | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
chisel-template
Posts with mentions or reviews of chisel-template.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-02-11.
-
I see that many open riscv cores use Scala that generate verilog. Is this common practice?
Also it's not hard to start, there is a template provided by Chisel devs at https://github.com/freechipsproject/chisel-template or my own at https://github.com/carlosedp/chisel-template.
rocket-chip
Posts with mentions or reviews of rocket-chip.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-03-08.
-
Recommendations for RISC-V on FPGA
Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?
-
RISC-V Pushes into the Mainstream
You could do a trial build of an in-order Rocket RISC-V core [1] to see how much space it takes up.
[1] https://github.com/chipsalliance/rocket-chip
- Can anyone explain simply how OpenSource the RISC-V actually is?
-
Stages of prototyping a RISC-V processor on an FPGA?
My definition of a RISC CPU is one that has a reduced instruction set. In other words, the category of CPU is defined by the size of the instruction set, not in how it is implemented. Consider for example RISC-V CPUs. These are defined by their open instruction set alone, in spite of the fact that many implementations of RISC-V CPUs exist: some pipelined, and some not.
- FPGA for RISC-V Processor
-
How are modern processors and their architecture designed?
More complex CPUs are typically completely out of scope for hand coding, therefore you can implement generators like: https://github.com/chipsalliance/rocket-chip
-
Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'"
We don't have Sifive's specifically but we do have the open source cores they've historically used to design their cores: https://github.com/riscv-boom/riscv-boom https://github.com/chipsalliance/rocket-chip
-
Project ideas for RISC-V?
This would allow you to experiment with your own chip or something like [the RocketChip generator](https://github.com/chipsalliance/rocket-chip).
-
Question: Does the 32bit version of Rocket still supports FPU
https://github.com/chipsalliance/rocket-chip/blob/c7da610430f51b02ebda37f3d444674dc8f2adbf/src/main/scala/system/Configs.scala#L28
-
The First Affordable RISC-V Computer Designed to Run Linux
I don't know about the u74 specifically, but sifive does seem to invest in a open source risc-v core called rocket-chip.
What are some alternatives?
When comparing chisel-template and rocket-chip you can also consider the following projects:
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
OpenROAD - OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
chisel-template - A template project for beginning new Chisel work
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
Cores-VeeR-EH1 - VeeR EH1 core
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
opentitan - OpenTitan: Open source silicon root of trust
Cores-VeeR-EL2 - VeeR EL2 Core
chisel-template vs riscv-boom
rocket-chip vs riscv-boom
chisel-template vs OpenROAD
rocket-chip vs chipyard
chisel-template vs chisel-template
rocket-chip vs openlane
rocket-chip vs picorv32
rocket-chip vs skywater-pdk
rocket-chip vs Cores-VeeR-EH1
rocket-chip vs fusesoc
rocket-chip vs opentitan
rocket-chip vs Cores-VeeR-EL2