I see that many open riscv cores use Scala that generate verilog. Is this common practice?

• XiangShan

  32 4,318 9.9 Scala

  Open-source high-performance RISC-V processor

  

Here’s a good example of one: https://github.com/OpenXiangShan/XiangShan

• chisel-template

  1 529 6.5 Scala

  A template project for beginning new Chisel work

  

Also it's not hard to start, there is a template provided by Chisel devs at https://github.com/freechipsproject/chisel-template or my own at https://github.com/carlosedp/chisel-template.

• InfluxDB

  www.influxdata.com featured

  Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  

• chisel-template

  1 4 10.0 Scala

  Chisel HDL Template Repository (by carlosedp)

Also it's not hard to start, there is a template provided by Chisel devs at https://github.com/freechipsproject/chisel-template or my own at https://github.com/carlosedp/chisel-template.

• OpenROAD

  7 1,328 10.0 Verilog

  OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

  

If you're interested in tools, I highly recommend going through the (Google-supported) OpenROAD toolset - these guys are building up a open-source infrastructure for the full digital flow: https://theopenroadproject.org/ .

Suggest a related project