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I see that many open riscv cores use Scala that generate verilog. Is this common practice?
4 projects | /r/RISCV | 11 Feb 2023

Also it's not hard to start, there is a template provided by Chisel devs at https://github.com/freechipsproject/chisel-template or my own at https://github.com/carlosedp/chisel-template.

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carlosedp/chisel-template is an open source project licensed under BSD 3-clause "New" or "Revised" License which is an OSI approved license.

The primary programming language of chisel-template is Scala.

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