basys3_fpga_sandbox
libsv
| basys3_fpga_sandbox | libsv | |
|---|---|---|
| 1 | 2 | |
| 0 | 19 | |
| - | - | |
| 10.0 | 3.6 | |
| over 1 year ago | about 2 years ago | |
| SystemVerilog | SystemVerilog | |
| - | MIT License |
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basys3_fpga_sandbox
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My first FSM in FPGA
Sure, https://github.com/martinKindall/basys3_fpga_sandbox/blob/main/sources_1/new/FourLedFSM.sv
libsv
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Skid Buffer
https://github.com/bensampson5/libsv/blob/main/libsv/fifos/skid_buffer.svhttps://libsv.readthedocs.io/en/latest/skid_buffer.html
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What should a modern IP library look like?
If you're interested in checking that out here's the link to the GitHub page for LibSV: https://github.com/bensampson5/libsv.
What are some alternatives?
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
risc-v-single-cycle - A Single Cycle Risc-V 32 bit CPU
DFHDL - DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
cheshire - A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
ulm-on-ice - ULM (Ulm Lecture Machine) on ice40
FPGA-Video-Processing - Realtime video processing w/ Gaussian + Sobel Filters targeting Artix-7 FPGA
opentitan - OpenTitan: Open source silicon root of trust
eurorack-pmod - Hardware and gateware for getting started in FPGA-based audio synthesis with open source tools.
VHDL_Lib - Library of VHDL components that are useful in larger designs.