anakin-language-server
hdl_checker
| anakin-language-server | hdl_checker | |
|---|---|---|
| 1 | 4 | |
| 34 | 183 | |
| - | - | |
| 6.8 | 0.0 | |
| 3 months ago | 4 months ago | |
| Python | Python | |
| GNU General Public License v3.0 only | GNU General Public License v3.0 only |
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anakin-language-server
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Performant alternative to pyright?
Try this https://github.com/muffinmad/anakin-language-server
hdl_checker
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Any better options than Sigasi?
I've written a LSP that uses modelsim, ghdl or Vivado to do error checking: https://github.com/suoto/hdl_checker
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What Editor is Everyone Using for FPGA design? (2021)
NeoVim + CoC + hdl_checker
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VHDL native lsp
As others mentioned, rust_hdl and ghdl ls are worth checking out. If your project has both VHDL and Verilog/SystemVerilog, might be worth checking https://github.com/suoto/hdl_checker (disclaimer, I'm the author). It's got less LS features than the other two but if you use it with modelsim it'll provide mixed language syntax check.
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IDE / Editor of choice
Specifically for HDL-files a lot of progress has been made in the last couple of years on lsp-mode and external LSP servers for code analysis of both VHDL and SystemVerilog. For SV I use the https://github.com/suoto/hdl_checker server that passes the code you are working on live to the Linting engine in Questa/ModelSim and marks the warning lines in the editor. It's nice to get immediate feedback on missing semicolons etc. although it still has a hard time handling large projects.
What are some alternatives?
Elpy - Emacs Python Development Environment
completor.vim - Async completion framework made ease.
deoplete-jedi - deoplete.nvim source for Python
rust_hdl
hy-language-server - Hy Language Server built using Jedhy. works only under Hy1.0a1. For the recent version of Hy, please use https://github.com/sakuraiyuta/hyuga instead.
veridian - A SystemVerilog Language Server
ffi-navigator
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
edalize - An abstraction library for interfacing EDA tools
cocotb-bus - Pre-packaged testbenching tools and reusable bus interfaces for cocotb